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authorVille Syrjälä <ville.syrjala@linux.intel.com>2023-06-08 23:30:49 +0300
committerVille Syrjälä <ville.syrjala@linux.intel.com>2023-06-13 19:04:25 +0300
commita43d92812077b15c8e3bfdf80dc9d8596b503c60 (patch)
treecb4c8decf5d94797efcb5497de6bc6554c537f8d
parentd4121327ac6af65327c1ae90bac89e1575f0f277 (diff)
drm/i915/dsi: Gate DSI clocks earlier
The clock gating step is in the wrong spot compared to the TGL+ bspec sequence. Move it the right place. Windows also seems to use the TGL+ order here always. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230608203057.23759-6-ville.syrjala@linux.intel.com
-rw-r--r--drivers/gpu/drm/i915/display/icl_dsi.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 6d60197cc9f1..973215bec3c1 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1110,6 +1110,8 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
/* enable DDI buffer */
gen11_dsi_enable_ddi_buffer(encoder);
+ gen11_dsi_gate_clocks(encoder);
+
gen11_dsi_setup_timings(encoder, crtc_state);
/* Since transcoder is configured to take events from GPIO */
@@ -1120,9 +1122,6 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
/* Step (4h, 4i, 4j, 4k): Configure transcoder */
gen11_dsi_configure_transcoder(encoder, crtc_state);
-
- /* Step 4l: Gate DDI clocks */
- gen11_dsi_gate_clocks(encoder);
}
static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)