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authorLucas Stach <l.stach@pengutronix.de>2023-06-07 14:58:41 +0200
committerLucas Stach <l.stach@pengutronix.de>2024-01-23 10:20:20 +0100
commitb0da08559c749ddc0e9a6e378b292ffa6845fb01 (patch)
tree27558a987c15b7fda0ddbac3f7c316ee0b20fae1
parent9e2e8a5113bf452081cb1f6a13617e36f5298cbf (diff)
drm/etnaviv: disable MLCG and pulse eater on GPU reset
Module level clock gating and the pulse eater might interfere with the GPU reset, as they both have the potential to stop the clock and thus reset propagation to parts of the GPU. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
-rw-r--r--drivers/gpu/drm/etnaviv/etnaviv_gpu.c13
1 files changed, 12 insertions, 1 deletions
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index 9276756e1397..1dcfa23db3be 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@ -513,8 +513,19 @@ static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
timeout = jiffies + msecs_to_jiffies(1000);
while (time_is_after_jiffies(timeout)) {
- /* enable clock */
unsigned int fscale = 1 << (6 - gpu->freq_scale);
+ u32 pulse_eater = 0x01590880;
+
+ /* disable clock gating */
+ gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, 0x0);
+
+ /* disable pulse eater */
+ pulse_eater |= BIT(17);
+ gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
+ pulse_eater |= BIT(0);
+ gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
+
+ /* enable clock */
control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
etnaviv_gpu_load_clock(gpu, control);