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authorCyrille Pitchen <cyrille.pitchen@atmel.com>2017-07-06 11:35:25 +0300
committerAlexandre Belloni <alexandre.belloni@free-electrons.com>2017-07-17 11:09:33 +0200
commitb23612d1e10da036a6efaddea3dc7cfb7ddc6799 (patch)
tree6ce587886633ba5b9033487fb722c3683ab90e3c
parent5771a8c08880cdca3bfb4a3fc6d309d6bba20877 (diff)
ARM: dts: at91: sama5d2: add QSPI nodes
This patch adds DT nodes for sama5d2 QSPI controllers. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> [claudiu.beznea@microchip.com: change subject to match the desired prefix] Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
-rw-r--r--arch/arm/boot/dts/sama5d2.dtsi22
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index cc06da394366..71e9d83b10de 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -954,6 +954,28 @@
};
};
+ qspi0: spi@f0020000 {
+ compatible = "atmel,sama5d2-qspi";
+ reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
+ reg-names = "qspi_base", "qspi_mmap";
+ interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&qspi0_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ qspi1: spi@f0024000 {
+ compatible = "atmel,sama5d2-qspi";
+ reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>;
+ reg-names = "qspi_base", "qspi_mmap";
+ interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&qspi1_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
sha@f0028000 {
compatible = "atmel,at91sam9g46-sha";
reg = <0xf0028000 0x100>;