diff options
| author | Chris Morgan <macromorgan@hotmail.com> | 2022-12-01 14:36:53 -0600 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2023-01-10 23:15:16 +0100 |
| commit | b8e3a0ff7674273b83c382b278bec49db7460e67 (patch) | |
| tree | 922e38a6938a27f51409308aed743de8b56c3934 | |
| parent | 0d4343988194a8336f2df8d2df766074a733b2c8 (diff) | |
arm64: dts: rockchip: don't set cpll rate for Odroid Go
The Odroid Go Advance devicetree tries to set the rate for the cpll
clock to 17MHz, which is not a supported rate. This fails, and triggers
the error of "clk: couldn't set cpll clk rate to 17000000 (-22),
current rate: 17000000" in the dmesg log. Remove the incorrect rate.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Link: https://lore.kernel.org/r/20221201203655.1245-3-macroalpha82@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi index 60063f4bb366..802be64626d6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi @@ -192,14 +192,12 @@ assigned-clocks = <&cru PLL_NPLL>, <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, - <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>, - <&cru PLL_CPLL>; + <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>; assigned-clock-rates = <1188000000>, <200000000>, <200000000>, <150000000>, <150000000>, - <100000000>, <200000000>, - <17000000>; + <100000000>, <200000000>; }; &display_subsystem { |