diff options
| author | Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2018-08-27 21:54:35 +0300 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2018-09-13 09:47:45 +0200 |
| commit | c6eb20473f0b296c671dc6f7a7766ea6bedf2d59 (patch) | |
| tree | fcc5d1f7d9359346631e3c47afcd63f4a10544b5 | |
| parent | ffa967e24c5817b48a3d5ecea2c12b9cdd807f0c (diff) | |
arm64: dts: renesas: condor: add PCIe support
Enable PCIe PHY and PCIEC and specify the PCIe bus clock for the Condor
board.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts index 59db4c152fb8..fe2e2c051cc9 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts +++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts @@ -223,6 +223,18 @@ status = "okay"; }; +&pciec { + status = "okay"; +}; + +&pcie_bus_clk { + clock-frequency = <100000000>; +}; + +&pcie_phy { + status = "okay"; +}; + &pfc { avb_pins: avb { groups = "avb_mdio", "avb_rgmii"; |