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| author | Arnd Bergmann <arnd@arndb.de> | 2023-05-26 16:28:43 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2023-05-26 16:28:56 +0200 |
| commit | c98d58987931764b610115e4fbd1df702b2a959e (patch) | |
| tree | 377fa245ba8db99f7d7527b8721815bafc68d298 | |
| parent | 1bf42cfed0e68543e09dfa8f15b478b2fe3824c5 (diff) | |
| parent | e2b96ceb554ec964e536dd443217d514684f6c49 (diff) | |
Merge tag 's32g2-dt-6.5' of https://github.com/chesterlintw/linux-s32g into soc/dt
DT changes for v6.5:
- Add missing cache properties for s32g2 and s32v234.
* tag 's32g2-dt-6.5' of https://github.com/chesterlintw/linux-s32g:
arm64: dts: s32: add missing cache properties
Link: https://lore.kernel.org/r/ZHC8PO8lDjTae7nV@linux-8mug
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/s32g2.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/s32v234.dtsi | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index d8c82da88ca0..5ac1cc9ff50e 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -53,11 +53,13 @@ cluster0_l2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster1_l2: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/freescale/s32v234.dtsi b/arch/arm64/boot/dts/freescale/s32v234.dtsi index 3e306218d533..42409ec56792 100644 --- a/arch/arm64/boot/dts/freescale/s32v234.dtsi +++ b/arch/arm64/boot/dts/freescale/s32v234.dtsi @@ -62,11 +62,13 @@ cluster0_l2_cache: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster1_l2_cache: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; |