diff options
| author | Vinay Belgaumkar <vinay.belgaumkar@intel.com> | 2023-11-09 11:21:48 -0800 |
|---|---|---|
| committer | John Harrison <John.C.Harrison@Intel.com> | 2023-11-15 17:09:48 -0800 |
| commit | d7b4832cbeb85075293b1211a9c89fad4fdda1f1 (patch) | |
| tree | 44d804b14c6f1c2b8db31307daa0ee504a9898ce | |
| parent | 968853033d8aa4dbb80fbafa6f5d9b6a0ea21272 (diff) | |
drm/i915: Read a shadowed mmio register for ggtt flush
We read RENDER_HEAD as a part of the flush. If GT is in
deeper sleep states, this could lead to read errors since we are
not using a forcewake. Safer to read a shadowed register instead.
Cc: John Harrison <john.c.harrison@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231109192148.475156-1-vinay.belgaumkar@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_gt.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index ed32bf5b1546..ea814ea5f700 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -451,7 +451,7 @@ void intel_gt_flush_ggtt_writes(struct intel_gt *gt) spin_lock_irqsave(&uncore->lock, flags); intel_uncore_posting_read_fw(uncore, - RING_HEAD(RENDER_RING_BASE)); + RING_TAIL(RENDER_RING_BASE)); spin_unlock_irqrestore(&uncore->lock, flags); } } |