diff options
| author | Swati Agarwal <swati.agarwal@amd.com> | 2023-11-14 15:53:21 +0530 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2023-12-07 14:08:44 +0100 |
| commit | dd69bd870998648c53fb11ea152c6b960b870b0b (patch) | |
| tree | 8afe4fd758a0546d6fb679c5c1fbf37bcfff6285 | |
| parent | 43658a542ebf13f1bb80cfaa8ae58f061d0d71b0 (diff) | |
dt-bindings: mmc: arasan,sdci: Add gate property for Xilinx platforms
Add gate property in example node for Xilinx platforms which will be used
to ungate the DLL clock. DLL clock is required for higher frequencies like
50MHz, 100MHz and 200MHz.
DLL clock is automatically selected by the SD controller when the SD
output clock frequency is more than 25 MHz.
Signed-off-by: Swati Agarwal <swati.agarwal@amd.com>
Co-developed-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20231114102321.1147951-1-sai.krishna.potthuri@amd.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| -rw-r--r-- | Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml index 3e99801f77d2..9075add020bf 100644 --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml @@ -226,8 +226,8 @@ examples: interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0xff160000 0x1000>; - clocks = <&clk200>, <&clk200>; - clock-names = "clk_xin", "clk_ahb"; + clocks = <&clk200>, <&clk200>, <&clk1200>; + clock-names = "clk_xin", "clk_ahb", "gate"; clock-output-names = "clk_out_sd0", "clk_in_sd0"; #clock-cells = <1>; clk-phase-sd-hs = <63>, <72>; @@ -239,8 +239,8 @@ examples: interrupt-parent = <&gic>; interrupts = <0 126 4>; reg = <0xf1040000 0x10000>; - clocks = <&clk200>, <&clk200>; - clock-names = "clk_xin", "clk_ahb"; + clocks = <&clk200>, <&clk200>, <&clk1200>; + clock-names = "clk_xin", "clk_ahb", "gate"; clock-output-names = "clk_out_sd0", "clk_in_sd0"; #clock-cells = <1>; clk-phase-sd-hs = <132>, <60>; |