diff options
author | Levin Du <djw@t-chip.com.cn> | 2021-07-09 16:01:26 +0800 |
---|---|---|
committer | Heiko Stuebner <heiko@sntech.de> | 2021-09-15 17:50:14 +0200 |
commit | e05e45e853e2c278aec5165e37deaa1132aad196 (patch) | |
tree | f97db37b5b9ef0d81aa634c81b6c80ec3db2a340 | |
parent | 9fe28eedd253040faea5a67dcb7d47af4bf9affd (diff) |
arm64: dts: rockchip: add support for Firefly ROC-RK3328-PC
ROC-RK3328-PC is the board inside the portable Firefly Station M1
Geek PC. As a redesign after the ROC-RK3328-CC, it uses TypeC as
power input and OTG port, embedded with eMMC 5.1 storage and a
SDIO WiFi/BT chip (RTL8723DS).
- Rockchip RK3328 SoC
- 2/4GB LPDDR3 RAM
- 16/32/64/128GB eMMC 5.1
- TF card slot
- USB 3.0 Port x 1, USB 2.0 Port x 1, TypeC Port x 1 (Power/OTG)
- HDMI
- Gigabit Ethernet
- WiFi: RTL8723DS
- Audio: RK3328
- Key: Power, Reset, Recovery
- LED: POWER, USER
- IR
Signed-off-by: Levin Du <djw@t-chip.com.cn>
Link: https://lore.kernel.org/r/20210709080126.17045-3-djw@t-chip.com.cn
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-rw-r--r-- | arch/arm64/boot/dts/rockchip/Makefile | 1 | ||||
-rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts | 110 |
2 files changed, 111 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 7fdb41de01ec..46652b6d7c4d 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lion-haikou.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts new file mode 100644 index 000000000000..e3e3984d01d4 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2021 T-Chip Intelligent Technology Co., Ltd + +/dts-v1/; + +#include <dt-bindings/input/input.h> + +#include "rk3328-roc-cc.dts" + +/ { + model = "Firefly ROC-RK3328-PC"; + compatible = "firefly,roc-rk3328-pc", "rockchip,rk3328"; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1750000>; + + /* This button is unpopulated out of the factory. */ + button-recovery { + label = "Recovery"; + linux,code = <KEY_VENDOR>; + press-threshold-microvolt = <10000>; + }; + }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; + linux,rc-map-name = "rc-khadas"; + pinctrl-names = "default"; + pinctrl-0 = <&ir_int>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_en>, <&wifi_host_wake>; + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + }; +}; + +&codec { + mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>; +}; + +&gpu { + mali-supply = <&vdd_logic>; +}; + +&pinctrl { + ir { + ir_int: ir-int { + rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmcio { + sdio_per_pin: sdio-per-pin { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wifi { + wifi_en: wifi-en { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_host_wake: wifi-host-wake { + rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_4ma>; + }; + + bt_rst: bt-rst { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_en: bt-en { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmic_int_l { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; +}; + +&rk805 { + interrupt-parent = <&gpio0>; + interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>; +}; + +&saradc { + vref-supply = <&vcc_18>; + status = "okay"; +}; + +&usb20_host_drv { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; +}; + +&vcc_host1_5v { + gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; +}; + +&vcc_sdio { + gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio_per_pin>; +}; |