diff options
| author | Rob Herring <robh@kernel.org> | 2020-05-12 15:45:39 -0500 |
|---|---|---|
| committer | Rob Herring <robh@kernel.org> | 2020-05-14 14:42:54 -0500 |
| commit | e2f233ec155360d1cfff19cde77ffd4785d571da (patch) | |
| tree | 6829cde39dedd45c5bf0dbf739cfcbe428bad935 | |
| parent | 65994c09bc66d7241be2f7d6eb3b43f894ba2db0 (diff) | |
spi: dt-bindings: sifive: Add missing 2nd register region
The 'reg' description and example have a 2nd register region for memory
mapped flash, but the schema says there is only 1 region. Fix this.
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: linux-spi@vger.kernel.org
Cc: linux-riscv@lists.infradead.org
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Paul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: Rob Herring <robh@kernel.org>
| -rw-r--r-- | Documentation/devicetree/bindings/spi/spi-sifive.yaml | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/Documentation/devicetree/bindings/spi/spi-sifive.yaml b/Documentation/devicetree/bindings/spi/spi-sifive.yaml index 28040598bfae..fb583e57c1f2 100644 --- a/Documentation/devicetree/bindings/spi/spi-sifive.yaml +++ b/Documentation/devicetree/bindings/spi/spi-sifive.yaml @@ -32,11 +32,10 @@ properties: https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi reg: - maxItems: 1 - - description: - Physical base address and size of SPI registers map - A second (optional) range can indicate memory mapped flash + minItems: 1 + items: + - description: SPI registers region + - description: Memory mapped flash region interrupts: maxItems: 1 |