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authorDmitry Osipenko <digetx@gmail.com>2020-11-04 19:48:41 +0300
committerKrzysztof Kozlowski <krzk@kernel.org>2020-11-06 19:29:08 +0100
commite51a59f079c546b8b5c31604ad98e86b06ec93e9 (patch)
tree75e8908de61a8932a6c34fe4de2fa408267d09c9
parent21d3cdd0391bb01b348a47ec117eff3b9615d3a9 (diff)
dt-bindings: memory: tegra20: emc: Document nvidia, memory-controller property
Tegra20 External Memory Controller talks to DRAM chips and it needs to be reprogrammed when memory frequency changes. Tegra Memory Controller sits behind EMC and these controllers are tightly coupled. This patch adds the new phandle property which allows to properly express connection of EMC and MC hardware in a device-tree, it also put the Tegra20 EMC binding on par with Tegra30+ EMC bindings, which is handy to have. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201104164923.21238-6-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
-rw-r--r--Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt2
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt
index 567cffd37f3f..1b0d4417aad8 100644
--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt
@@ -12,6 +12,7 @@ Properties:
irrespective of ram-code configuration.
- interrupts : Should contain EMC General interrupt.
- clocks : Should contain EMC clock.
+- nvidia,memory-controller : Phandle of the Memory Controller node.
Child device nodes describe the memory settings for different configurations and clock rates.
@@ -24,6 +25,7 @@ Example:
reg = <0x7000f400 0x400>;
interrupts = <0 78 0x04>;
clocks = <&tegra_car TEGRA20_CLK_EMC>;
+ nvidia,memory-controller = <&mc>;
}