summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorGiulio Benetti <giulio.benetti@micronovasrl.com>2018-02-28 17:46:53 +0100
committerMaxime Ripard <maxime.ripard@bootlin.com>2018-03-01 10:41:27 +0100
commite64b6afa98f3629d0c0c46233bbdbe8acdb56f06 (patch)
treec3a92ee1cb2e64f09ab710b02b8d3d6ad08f55c4
parent9a191b114906457c4b2494c474f58ae4142d4e67 (diff)
drm/sun4i: Fix dclk_set_phase
Phase value is not shifted before writing. Shift left of 28 bits to fit right bits Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/1519836413-35023-1-git-send-email-giulio.benetti@micronovasrl.com
-rw-r--r--drivers/gpu/drm/sun4i/sun4i_dotclock.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/sun4i/sun4i_dotclock.c b/drivers/gpu/drm/sun4i/sun4i_dotclock.c
index 023f39bda633..e36004fbe453 100644
--- a/drivers/gpu/drm/sun4i/sun4i_dotclock.c
+++ b/drivers/gpu/drm/sun4i/sun4i_dotclock.c
@@ -132,10 +132,13 @@ static int sun4i_dclk_get_phase(struct clk_hw *hw)
static int sun4i_dclk_set_phase(struct clk_hw *hw, int degrees)
{
struct sun4i_dclk *dclk = hw_to_dclk(hw);
+ u32 val = degrees / 120;
+
+ val <<= 28;
regmap_update_bits(dclk->regmap, SUN4I_TCON0_IO_POL_REG,
GENMASK(29, 28),
- degrees / 120);
+ val);
return 0;
}