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authorPeng Fan <peng.fan@nxp.com>2020-03-19 15:49:50 +0800
committerJassi Brar <jaswinder.singh@linaro.org>2020-03-19 23:02:39 -0500
commiteabb8b8cfe96874f5801b5017bd3c3fa708b8309 (patch)
tree58e4cf2089c6a2ac83ee04ecb210a61f16412e6a
parentc9ea564f3d9dd20d88bd34f40a6ff6d31a0d7e8c (diff)
dt-bindings: mailbox: imx-mu: add SCU MU support
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A cores from hardware design, it could not be reused for other purpose. To use SCU MU more effectivly, add "fsl,imx8-scu-mu" compatile to support fast IPC. Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
-rw-r--r--Documentation/devicetree/bindings/mailbox/fsl,mu.txt2
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
index 9c43357c5924..31486c9f6443 100644
--- a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
+++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
@@ -23,6 +23,8 @@ Required properties:
be included together with SoC specific compatible.
There is a version 1.0 MU on imx7ulp, use "fsl,imx7ulp-mu"
compatible to support it.
+ To communicate with i.MX8 SCU, "fsl,imx8-mu-scu" could be
+ used for fast IPC
- reg : Should contain the registers location and length
- interrupts : Interrupt number. The interrupt specifier format depends
on the interrupt controller parent.