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authorShawn Guo <shawn.guo@freescale.com>2014-05-19 22:23:43 +0800
committerShawn Guo <shawn.guo@freescale.com>2014-07-18 16:10:07 +0800
commitee18a7154ee080af82cb81e93f1fdcbd44176d5e (patch)
treefb5e3fc69ce0914bd6c4371cd3ba6f946b6398fe
parent1f84e906f86968333eb00ed88b7f7e7a37b17589 (diff)
ARM: imx5: retrieve iim base from device tree
Instead of using static define and mapping, the patch changes imx5 code that reads chip revision from IIM to retrieve base address from device tree and use dynamic mapping. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
-rw-r--r--arch/arm/mach-imx/cpu-imx5.c25
1 files changed, 21 insertions, 4 deletions
diff --git a/arch/arm/mach-imx/cpu-imx5.c b/arch/arm/mach-imx/cpu-imx5.c
index c1c99a72c6a1..3403bac94a31 100644
--- a/arch/arm/mach-imx/cpu-imx5.c
+++ b/arch/arm/mach-imx/cpu-imx5.c
@@ -16,6 +16,8 @@
#include <linux/init.h>
#include <linux/module.h>
#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
#include "hardware.h"
#include "common.h"
@@ -24,10 +26,26 @@ static int mx5_cpu_rev = -1;
#define IIM_SREV 0x24
+static u32 imx5_read_srev_reg(const char *compat)
+{
+ void __iomem *iim_base;
+ struct device_node *np;
+ u32 srev;
+
+ np = of_find_compatible_node(NULL, NULL, compat);
+ iim_base = of_iomap(np, 0);
+ WARN_ON(!iim_base);
+
+ srev = readl(iim_base + IIM_SREV) & 0xff;
+
+ iounmap(iim_base);
+
+ return srev;
+}
+
static int get_mx51_srev(void)
{
- void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR);
- u32 rev = readl(iim_base + IIM_SREV) & 0xff;
+ u32 rev = imx5_read_srev_reg("fsl,imx51-iim");
switch (rev) {
case 0x0:
@@ -77,8 +95,7 @@ int __init mx51_neon_fixup(void)
static int get_mx53_srev(void)
{
- void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR);
- u32 rev = readl(iim_base + IIM_SREV) & 0xff;
+ u32 rev = imx5_read_srev_reg("fsl,imx53-iim");
switch (rev) {
case 0x0: