diff options
| author | Sandipan Das <sandipan.das@amd.com> | 2022-05-19 15:33:34 +0530 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2022-06-13 10:15:14 +0200 |
| commit | f0fe9f3c7abcc946a676dfb295478c50312523c2 (patch) | |
| tree | 351b8fae0b663ec1b3b86e8e2916f3887b9d4634 | |
| parent | c390241a93260b377c84ad9e7cd5242adf667aac (diff) | |
perf/x86/amd/uncore: Add PerfMonV2 RDPMC assignments
The current RDPMC assignment scheme maps four DF PMCs and
six L3 PMCs from index 6 to 15.
If AMD Performance Monitoring Version 2 (PerfMonV2) is
supported, there may be additional DF counters available
which are mapped starting from index 16 i.e. just after
the L3 counters. Update the RDPMC assignments accordingly.
Signed-off-by: Sandipan Das <sandipan.das@amd.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/r/1359379ef34da760f108b075ac138ab082caa3ba.1652954372.git.sandipan.das@amd.com
| -rw-r--r-- | arch/x86/events/amd/uncore.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c index ff4238eff087..d568afc705d2 100644 --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -158,6 +158,16 @@ out: hwc->event_base_rdpmc = uncore->rdpmc_base + hwc->idx; hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; + /* + * The first four DF counters are accessible via RDPMC index 6 to 9 + * followed by the L3 counters from index 10 to 15. For processors + * with more than four DF counters, the DF RDPMC assignments become + * discontiguous as the additional counters are accessible starting + * from index 16. + */ + if (is_nb_event(event) && hwc->idx >= NUM_COUNTERS_NB) + hwc->event_base_rdpmc += NUM_COUNTERS_L3; + if (flags & PERF_EF_START) amd_uncore_start(event, PERF_EF_RELOAD); |