diff options
| author | H Hartley Sweeten <hsweeten@visionengravers.com> | 2014-06-20 13:28:46 -0700 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2014-06-26 20:11:16 -0400 |
| commit | f114b45a6b14682c55e8c2709e07b1ccf4d727a2 (patch) | |
| tree | 8e21f4522420d98fa68b0bb7851ba860ffa951fb | |
| parent | 860ba36cbeadee9064e2925be11dfb8368b9b25d (diff) | |
staging: comedi: s626: define CRA/CRB registers based on channel number
Start cleaning up the 'struct s626_enc_info' by redefining the my_cra
and my_crb members based on the comedi channel number.
Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| -rw-r--r-- | drivers/staging/comedi/drivers/s626.c | 24 | ||||
| -rw-r--r-- | drivers/staging/comedi/drivers/s626.h | 10 |
2 files changed, 15 insertions, 19 deletions
diff --git a/drivers/staging/comedi/drivers/s626.c b/drivers/staging/comedi/drivers/s626.c index 0838f8aa6951..91f96e30ab48 100644 --- a/drivers/staging/comedi/drivers/s626.c +++ b/drivers/staging/comedi/drivers/s626.c @@ -1322,8 +1322,8 @@ static const struct s626_enc_info s626_enc_chan_info[] = { .set_load_trig = s626_set_load_trig_a, .set_mode = s626_set_mode_a, .reset_cap_flags = s626_reset_cap_flags_a, - .my_cra = S626_LP_CR0A, - .my_crb = S626_LP_CR0B, + .my_cra = S626_LP_CRA(0), + .my_crb = S626_LP_CRB(0), .my_latch_lsw = S626_LP_CNTR0ALSW, .my_event_bits = S626_EVBITS(0), }, { @@ -1337,8 +1337,8 @@ static const struct s626_enc_info s626_enc_chan_info[] = { .set_load_trig = s626_set_load_trig_a, .set_mode = s626_set_mode_a, .reset_cap_flags = s626_reset_cap_flags_a, - .my_cra = S626_LP_CR1A, - .my_crb = S626_LP_CR1B, + .my_cra = S626_LP_CRA(1), + .my_crb = S626_LP_CRB(1), .my_latch_lsw = S626_LP_CNTR1ALSW, .my_event_bits = S626_EVBITS(1), }, { @@ -1352,8 +1352,8 @@ static const struct s626_enc_info s626_enc_chan_info[] = { .set_load_trig = s626_set_load_trig_a, .set_mode = s626_set_mode_a, .reset_cap_flags = s626_reset_cap_flags_a, - .my_cra = S626_LP_CR2A, - .my_crb = S626_LP_CR2B, + .my_cra = S626_LP_CRA(2), + .my_crb = S626_LP_CRB(2), .my_latch_lsw = S626_LP_CNTR2ALSW, .my_event_bits = S626_EVBITS(2), }, { @@ -1367,8 +1367,8 @@ static const struct s626_enc_info s626_enc_chan_info[] = { .set_load_trig = s626_set_load_trig_b, .set_mode = s626_set_mode_b, .reset_cap_flags = s626_reset_cap_flags_b, - .my_cra = S626_LP_CR0A, - .my_crb = S626_LP_CR0B, + .my_cra = S626_LP_CRA(3), + .my_crb = S626_LP_CRB(3), .my_latch_lsw = S626_LP_CNTR0BLSW, .my_event_bits = S626_EVBITS(3), }, { @@ -1382,8 +1382,8 @@ static const struct s626_enc_info s626_enc_chan_info[] = { .set_load_trig = s626_set_load_trig_b, .set_mode = s626_set_mode_b, .reset_cap_flags = s626_reset_cap_flags_b, - .my_cra = S626_LP_CR1A, - .my_crb = S626_LP_CR1B, + .my_cra = S626_LP_CRA(4), + .my_crb = S626_LP_CRB(4), .my_latch_lsw = S626_LP_CNTR1BLSW, .my_event_bits = S626_EVBITS(4), }, { @@ -1397,8 +1397,8 @@ static const struct s626_enc_info s626_enc_chan_info[] = { .set_load_trig = s626_set_load_trig_b, .set_mode = s626_set_mode_b, .reset_cap_flags = s626_reset_cap_flags_b, - .my_cra = S626_LP_CR2A, - .my_crb = S626_LP_CR2B, + .my_cra = S626_LP_CRA(5), + .my_crb = S626_LP_CRB(5), .my_latch_lsw = S626_LP_CNTR2BLSW, .my_event_bits = S626_EVBITS(5), }, diff --git a/drivers/staging/comedi/drivers/s626.h b/drivers/staging/comedi/drivers/s626.h index 33b72739c1cb..70557a00f88a 100644 --- a/drivers/staging/comedi/drivers/s626.h +++ b/drivers/staging/comedi/drivers/s626.h @@ -229,13 +229,9 @@ #define S626_LP_RDEDGSEL(x) (0x004c + (x) * 0x10) /* R: edge selection */ #define S626_LP_RDCAPSEL(x) (0x004e + (x) * 0x10) /* R: capture enable */ -/* Counter Registers (read/write): */ -#define S626_LP_CR0A 0x0000 /* 0A setup register. */ -#define S626_LP_CR0B 0x0002 /* 0B setup register. */ -#define S626_LP_CR1A 0x0004 /* 1A setup register. */ -#define S626_LP_CR1B 0x0006 /* 1B setup register. */ -#define S626_LP_CR2A 0x0008 /* 2A setup register. */ -#define S626_LP_CR2B 0x000A /* 2B setup register. */ +/* Counter registers (read/write): 0A 1A 2A 0B 1B 2B */ +#define S626_LP_CRA(x) (0x0000 + (((x) % 3) * 0x4)) +#define S626_LP_CRB(x) (0x0002 + (((x) % 3) * 0x4)) /* Counter PreLoad (write) and Latch (read) Registers: */ #define S626_LP_CNTR0ALSW 0x000C /* 0A lsw. */ |