diff options
| author | Marc Zyngier <maz@kernel.org> | 2019-07-31 17:29:33 +0100 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2019-08-20 10:23:35 +0100 |
| commit | 7f2481b39b4c776fb9c03081ffcfe81f4961601c (patch) | |
| tree | 6d0c5f6095ffa9a0672f97af2a67a60d4f0c1b37 /Documentation/arm64/silicon-errata.rst | |
| parent | 25edaed6c7feca8fded25348732c628283304364 (diff) | |
irqchip/gic-v3: Add quirks for HIP06/07 invalid GICD_TYPER erratum 161010803
It looks like the HIP06/07 SoCs have extra bits in their GICD_TYPER
registers, which confuse the GICv3.1 code (these systems appear to
expose ESPIs while they actually don't).
Detect these systems as early as possible and wipe the fields that
should be RES0 in the register.
Tested-by: John Garry <john.garry@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Diffstat (limited to 'Documentation/arm64/silicon-errata.rst')
| -rw-r--r-- | Documentation/arm64/silicon-errata.rst | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst index 3e57d09246e6..17ea3fecddaa 100644 --- a/Documentation/arm64/silicon-errata.rst +++ b/Documentation/arm64/silicon-errata.rst @@ -115,6 +115,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | Hisilicon | Hip0{6,7} | #161010701 | N/A | +----------------+-----------------+-----------------+-----------------------------+ +| Hisilicon | Hip0{6,7} | #161010803 | N/A | ++----------------+-----------------+-----------------+-----------------------------+ | Hisilicon | Hip07 | #161600802 | HISILICON_ERRATUM_161600802 | +----------------+-----------------+-----------------+-----------------------------+ | Hisilicon | Hip08 SMMU PMCG | #162001800 | N/A | |