Merge tag 'riscv-dt-for-v6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt

RISC-V Devicetrees for v6.5

StarFive:
Watchdog nodes for both the JH7110 & its forerunner, the JH7100. PMU, P
being power, support for the JH7110. PMIC and frequency scaling support
for the JH7110 equipped VisionFive 2.
Most of the DT bits for the JH7110, and the SBCs using it, are pending
support for one of the clock controllers, so it's a smaller set of
changes than I would have hoped for.

Misc:
Pick up some dt-binding cleanup that Palmer assigned to me & had no
uptake from the respective maintainers. My powers of estimation failed
me again, with part of my motivation for picking them up being the
addition of new platforms that ended up not making it. Hopefully next
window for those, as they were relatively close.
Exclude the Allwinner and Renesas subdirectories from the Misc.
MAINTAINERS entry, since I do not take care of those.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

* tag 'riscv-dt-for-v6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
  riscv: dts: starfive: Add cpu scaling for JH7110 SoC
  riscv: dts: starfive: Enable axp15060 pmic for cpufreq
  dt-bindings: interrupt-controller: sifive,plic: Sort compatible values
  dt-bindings: timer: sifive,clint: Clean up compatible value section
  riscv: dts: starfive: jh7110: Add watchdog node
  riscv: dts: starfive: jh7100: Add watchdog node
  riscv: dts: starfive: Add PMU controller node
  MAINTAINERS: exclude maintained subdirs in RISC-V misc DT entry

Link: https://lore.kernel.org/r/20230612-fasting-floss-0bc05a08bc7a@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

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