Merge tag 'devicetree-for-6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

Pull devicetree updates from Rob Herring:
 "Bindings:

   - Convert Qcom IOMMU, Amlogic timer, Freescale sec-v4.0, Toshiba
     TC358764 display bridge, Parade PS8622 display bridge, and Xilinx
     FPGA bindings to DT schema format

   - Add qdu1000 and sa8775p SoC support to Qcom PDC interrupt
     controller

   - Add MediaTek MT8365 UART and SYSIRQ bindings

   - Add Arm Cortex-A78C and X1C core compatibles

   - Add vendor prefix for Novatek

   - Remove bindings for stih415, sti416, stid127 platforms

   - Drop uneeded quotes in schema files. This is preparation for
     yamllint checking quoting for us.

   - Add missing (unevaluated|additional)Properties constraints on child
     node schemas

   - Clean-up schema comments formatting

   - Fix I2C and SPI node bus names in schema examples

   - Clean-up some display compatibles schema syntax

   - Fix incorrect references to lvds.yaml

   - Gather all cache controller bindings in a common directory

  DT core:

   - Convert unittest to new void .remove platform device hook

   - kerneldoc fixes for DT address of_pci_range_to_resource/
     of_address_to_resource functions"

* tag 'devicetree-for-6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (46 commits)
  dt-bindings: rng: Drop unneeded quotes
  dt-bindings: arm/soc: mediatek: Drop unneeded quotes
  dt-bindings: soc: qcom: Drop unneeded quotes
  dt-bindings: i2c: samsung: Fix 'deprecated' value
  dt-bindings: display: Fix lvds.yaml references
  dt-bindings: display: simplify compatibles syntax
  dt-bindings: display: mediatek: simplify compatibles syntax
  dt-bindings: drm/bridge: ti-sn65dsi86: Fix the video-interfaces.yaml references
  dt-bindings: timer: Drop unneeded quotes
  dt-bindings: interrupt-controller: qcom,pdc: document qcom,qdu1000-pdc
  dt-bindings: interrupt-controller: qcom-pdc: add compatible for sa8775p
  dt-bindings: reset: remove stih415/stih416 reset
  dt-bindings: net: dwmac: sti: remove stih415/sti416/stid127
  dt-bindings: irqchip: sti: remove stih415/stih416 and stid127
  dt-bindings: iommu: Convert QCOM IOMMU to YAML
  dt-bindings: irqchip: ti,sci-inta: Add optional power-domains property
  dt-bindings: Add missing (unevaluated|additional)Properties on child node schemas
  of: address: Reshuffle to remove forward declarations
  of: address: Fix documented return value of of_pci_range_to_resource()
  of: address: Document return value of of_address_to_resource()
  ...

21 files changed, 34 insertions, 570 deletions

diff --git a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml
index eec190a96225..09c319f803ba 100644
--- a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml
+++ b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml
@@ -144,6 +144,7 @@ patternProperties:
       it is stricter and always has two compatibles.
     type: object
     $ref: '/schemas/simple-bus.yaml'
+    unevaluatedProperties: false
 
     properties:
       compatible:
diff --git a/Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml b/Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml
index b369b374fc4a..39e3c248f5b7 100644
--- a/Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml
+++ b/Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml
@@ -30,6 +30,7 @@ properties:
 
   clocks:
     type: object
+    additionalProperties: false
 
     properties:
       compatible:
@@ -47,6 +48,7 @@ properties:
 
   reset:
     type: object
+    additionalProperties: false
 
     properties:
       compatible:
@@ -63,6 +65,7 @@ properties:
 
   pwm:
     type: object
+    additionalProperties: false
 
     properties:
       compatible:
@@ -76,8 +79,6 @@ properties:
       - compatible
       - "#pwm-cells"
 
-    additionalProperties: false
-
 required:
   - compatible
   - mboxes
diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
index e287dcaec203..ff272e517d57 100644
--- a/Documentation/devicetree/bindings/arm/cpus.yaml
+++ b/Documentation/devicetree/bindings/arm/cpus.yaml
@@ -141,6 +141,7 @@ properties:
       - arm,cortex-a77
       - arm,cortex-a78
       - arm,cortex-a78ae
+      - arm,cortex-a78c
       - arm,cortex-a510
       - arm,cortex-a710
       - arm,cortex-a715
@@ -153,6 +154,7 @@ properties:
       - arm,cortex-r5
       - arm,cortex-r7
       - arm,cortex-x1
+      - arm,cortex-x1c
       - arm,cortex-x2
       - arm,cortex-x3
       - arm,neoverse-e1
diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.yaml b/Documentation/devicetree/bindings/arm/l2c2x0.yaml
deleted file mode 100644
index 6b8f4d4fa580..000000000000
--- a/Documentation/devicetree/bindings/arm/l2c2x0.yaml
+++ /dev/null
@@ -1,242 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/arm/l2c2x0.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: ARM L2 Cache Controller
-
-maintainers:
-  - Rob Herring <robh@kernel.org>
-
-description: |+
-  ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/
-  PL220/PL310 and variants) based level 2 cache controller. All these various
-  implementations of the L2 cache controller have compatible programming
-  models (Note 1). Some of the properties that are just prefixed "cache-*" are
-  taken from section 3.7.3 of the Devicetree Specification which can be found
-  at:
-  https://www.devicetree.org/specifications/
-
-  Note 1: The description in this document doesn't apply to integrated L2
-    cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
-    integrated L2 controllers are assumed to be all preconfigured by
-    early secure boot code. Thus no need to deal with their configuration
-    in the kernel at all.
-
-allOf:
-  - $ref: /schemas/cache-controller.yaml#
-
-properties:
-  compatible:
-    oneOf:
-      - enum:
-          - arm,pl310-cache
-          - arm,l220-cache
-          - arm,l210-cache
-            # DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
-          - bcm,bcm11351-a2-pl310-cache
-            # For Broadcom bcm11351 chipset where an
-            # offset needs to be added to the address before passing down to the L2
-            # cache controller
-          - brcm,bcm11351-a2-pl310-cache
-            # Marvell Controller designed to be
-            # compatible with the ARM one, with system cache mode (meaning
-            # maintenance operations on L1 are broadcasted to the L2 and L2
-            # performs the same operation).
-          - marvell,aurora-system-cache
-            # Marvell Controller designed to be
-            # compatible with the ARM one with outer cache mode.
-          - marvell,aurora-outer-cache
-      - items:
-           # Marvell Tauros3 cache controller, compatible
-           # with arm,pl310-cache controller.
-          - const: marvell,tauros3-cache
-          - const: arm,pl310-cache
-
-  cache-level:
-    const: 2
-
-  cache-unified: true
-  cache-size: true
-  cache-sets: true
-  cache-block-size: true
-  cache-line-size: true
-
-  reg:
-    maxItems: 1
-
-  arm,data-latency:
-    description: Cycles of latency for Data RAM accesses. Specifies 3 cells of
-      read, write and setup latencies. Minimum valid values are 1. Controllers
-      without setup latency control should use a value of 0.
-    $ref: /schemas/types.yaml#/definitions/uint32-array
-    minItems: 2
-    maxItems: 3
-    items:
-      minimum: 0
-      maximum: 8
-
-  arm,tag-latency:
-    description: Cycles of latency for Tag RAM accesses. Specifies 3 cells of
-      read, write and setup latencies. Controllers without setup latency control
-      should use 0. Controllers without separate read and write Tag RAM latency
-      values should only use the first cell.
-    $ref: /schemas/types.yaml#/definitions/uint32-array
-    minItems: 1
-    maxItems: 3
-    items:
-      minimum: 0
-      maximum: 8
-
-  arm,dirty-latency:
-    description: Cycles of latency for Dirty RAMs. This is a single cell.
-    $ref: /schemas/types.yaml#/definitions/uint32
-    minimum: 1
-    maximum: 8
-
-  arm,filter-ranges:
-    description: <start length> Starting address and length of window to
-      filter. Addresses in the filter window are directed to the M1 port. Other
-      addresses will go to the M0 port.
-    $ref: /schemas/types.yaml#/definitions/uint32-array
-    items:
-      minItems: 2
-      maxItems: 2
-
-  arm,io-coherent:
-    description: indicates that the system is operating in an hardware
-      I/O coherent mode. Valid only when the arm,pl310-cache compatible
-      string is used.
-    type: boolean
-
-  interrupts:
-    # Either a single combined interrupt or up to 9 individual interrupts
-    minItems: 1
-    maxItems: 9
-
-  cache-id-part:
-    description: cache id part number to be used if it is not present
-      on hardware
-    $ref: /schemas/types.yaml#/definitions/uint32
-
-  wt-override:
-    description: If present then L2 is forced to Write through mode
-    type: boolean
-
-  arm,double-linefill:
-    description: Override double linefill enable setting. Enable if
-      non-zero, disable if zero.
-    $ref: /schemas/types.yaml#/definitions/uint32
-    enum: [0, 1]
-
-  arm,double-linefill-incr:
-    description: Override double linefill on INCR read. Enable
-      if non-zero, disable if zero.
-    $ref: /schemas/types.yaml#/definitions/uint32
-    enum: [0, 1]
-
-  arm,double-linefill-wrap:
-    description: Override double linefill on WRAP read. Enable
-      if non-zero, disable if zero.
-    $ref: /schemas/types.yaml#/definitions/uint32
-    enum: [0, 1]
-
-  arm,prefetch-drop:
-    description: Override prefetch drop enable setting. Enable if non-zero,
-      disable if zero.
-    $ref: /schemas/types.yaml#/definitions/uint32
-    enum: [0, 1]
-
-  arm,prefetch-offset:
-    description: Override prefetch offset value.
-    $ref: /schemas/types.yaml#/definitions/uint32
-    enum: [0, 1, 2, 3, 4, 5, 6, 7, 15, 23, 31]
-
-  arm,shared-override:
-    description: The default behavior of the L220 or PL310 cache
-      controllers with respect to the shareable attribute is to transform "normal
-      memory non-cacheable transactions" into "cacheable no allocate" (for reads)
-      or "write through no write allocate" (for writes).
-      On systems where this may cause DMA buffer corruption, this property must
-      be specified to indicate that such transforms are precluded.
-    type: boolean
-
-  arm,parity-enable:
-    description: enable parity checking on the L2 cache (L220 or PL310).
-    type: boolean
-
-  arm,parity-disable:
-    description: disable parity checking on the L2 cache (L220 or PL310).
-    type: boolean
-
-  marvell,ecc-enable:
-    description: enable ECC protection on the L2 cache
-    type: boolean
-
-  arm,outer-sync-disable:
-    description: disable the outer sync operation on the L2 cache.
-      Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that
-      will randomly hang unless outer sync operations are disabled.
-    type: boolean
-
-  prefetch-data:
-    description: |
-      Data prefetch. Value: <0> (forcibly disable), <1>
-      (forcibly enable), property absent (retain settings set by firmware)
-    $ref: /schemas/types.yaml#/definitions/uint32
-    enum: [0, 1]
-
-  prefetch-instr:
-    description: |
-      Instruction prefetch. Value: <0> (forcibly disable),
-      <1> (forcibly enable), property absent (retain settings set by
-      firmware)
-    $ref: /schemas/types.yaml#/definitions/uint32
-    enum: [0, 1]
-
-  arm,dynamic-clock-gating:
-    description: |
-      L2 dynamic clock gating. Value: <0> (forcibly
-      disable), <1> (forcibly enable), property absent (OS specific behavior,
-      preferably retain firmware settings)
-    $ref: /schemas/types.yaml#/definitions/uint32
-    enum: [0, 1]
-
-  arm,standby-mode:
-    description: L2 standby mode enable. Value <0> (forcibly disable),
-      <1> (forcibly enable), property absent (OS specific behavior,
-      preferably retain firmware settings)
-    $ref: /schemas/types.yaml#/definitions/uint32
-    enum: [0, 1]
-
-  arm,early-bresp-disable:
-    description: Disable the CA9 optimization Early BRESP (PL310)
-    type: boolean
-
-  arm,full-line-zero-disable:
-    description: Disable the CA9 optimization Full line of zero
-      write (PL310)
-    type: boolean
-
-required:
-  - compatible
-  - cache-unified
-  - reg
-
-additionalProperties: false
-
-examples:
-  - |
-    cache-controller@fff12000 {
-        compatible = "arm,pl310-cache";
-        reg = <0xfff12000 0x1000>;
-        arm,data-latency = <1 1 1>;
-        arm,tag-latency = <2 2 2>;
-        arm,filter-ranges = <0x80000000 0x8000000>;
-        cache-unified;
-        cache-level = <2>;
-        interrupts = <45>;
-    };
-
-...
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
index e997635e4fe4..ea98043c6ba3 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
@@ -1,8 +1,8 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: MediaTek Infrastructure System Configuration Controller
 
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index d1410345ef18..536f5a5ebd24 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -1,8 +1,8 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mmsys.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mmsys.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: MediaTek mmsys controller
 
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml
index 9fbeb626ab23..d89848a8f478 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml
@@ -1,8 +1,8 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: MediaTek PCIE Mirror Controller for MT7622
 
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml
index f7d578a171a4..28ded09d72e3 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml
@@ -1,8 +1,8 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-wed.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-wed.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: MediaTek Wireless Ethernet Dispatch Controller for MT7622
 
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wed-pcie.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wed-pcie.yaml
index 96221f51c1c3..82f64469a601 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wed-pcie.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wed-pcie.yaml
@@ -1,8 +1,8 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wed-pcie.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wed-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: MediaTek PCIE WED Controller for MT7986
 
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-clock.yaml
index cf1002c3efa6..7cd14b163abe 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-clock.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-clock.yaml
@@ -1,8 +1,8 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-clock.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: MediaTek Functional Clock Controller for MT8186
 
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
index 661047d26e11..64c769416690 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
@@ -1,8 +1,8 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-sys-clock.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-sys-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: MediaTek System Clock Controller for MT8186
 
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
index b57cc2e69efb..dff4c8e8fd4b 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
@@ -1,8 +1,8 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-clock.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: MediaTek Functional Clock Controller for MT8192
 
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
index 27f79175c678..8d608fddf3f9 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
@@ -1,8 +1,8 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-sys-clock.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-sys-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: MediaTek System Clock Controller for MT8192
 
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml
index d62d60181147..d17164b0b13e 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml
@@ -1,8 +1,8 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: MediaTek Functional Clock Controller for MT8195
 
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
index 95b6bdf99936..066c9b3d6ac9 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
@@ -1,8 +1,8 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-sys-clock.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-sys-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: MediaTek System Clock Controller for MT8195
 
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml
index ef62cbb13590..26158d0d72f3 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml
@@ -1,8 +1,8 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,pericfg.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,pericfg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: MediaTek Peripheral Configuration Controller
 
diff --git a/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt b/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt
deleted file mode 100644
index 0d244b999d10..000000000000
--- a/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-* Marvell Feroceon Cache
-
-Required properties:
-- compatible : Should be either "marvell,feroceon-cache" or
-  	       "marvell,kirkwood-cache".
-
-Optional properties:
-- reg        : Address of the L2 cache control register. Mandatory for
-  	       "marvell,kirkwood-cache", not used by "marvell,feroceon-cache"
-
-
-Example:
-		l2: l2-cache@20128 {
-			compatible = "marvell,kirkwood-cache";
-			reg = <0x20128 0x4>;
-		};
diff --git a/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt b/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt
deleted file mode 100644
index 31af1cbb60bd..000000000000
--- a/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-* Marvell Tauros2 Cache
-
-Required properties:
-- compatible : Should be "marvell,tauros2-cache".
-- marvell,tauros2-cache-features : Specify the features supported for the
-  tauros2 cache.
-  The features including
-    CACHE_TAUROS2_PREFETCH_ON       (1 << 0)
-    CACHE_TAUROS2_LINEFILL_BURST8   (1 << 1)
-  The definition can be found at
-  arch/arm/include/asm/hardware/cache-tauros2.h
-
-Example:
-	L2: l2-cache {
-		compatible = "marvell,tauros2-cache";
-		marvell,tauros2-cache-features = <0x3>;
-	};
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
deleted file mode 100644
index 02cc6894eb13..000000000000
--- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
+++ /dev/null
@@ -1,168 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/arm/msm/qcom,llcc.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Last Level Cache Controller
-
-maintainers:
-  - Bjorn Andersson <andersson@kernel.org>
-
-description: |
-  LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
-  that can be shared by multiple clients. Clients here are different cores in the
-  SoC, the idea is to minimize the local caches at the clients and migrate to
-  common pool of memory. Cache memory is divided into partitions called slices
-  which are assigned to clients. Clients can query the slice details, activate
-  and deactivate them.
-
-properties:
-  compatible:
-    enum:
-      - qcom,sc7180-llcc
-      - qcom,sc7280-llcc
-      - qcom,sc8180x-llcc
-      - qcom,sc8280xp-llcc
-      - qcom,sdm845-llcc
-      - qcom,sm6350-llcc
-      - qcom,sm7150-llcc
-      - qcom,sm8150-llcc
-      - qcom,sm8250-llcc
-      - qcom,sm8350-llcc
-      - qcom,sm8450-llcc
-      - qcom,sm8550-llcc
-
-  reg:
-    minItems: 2
-    maxItems: 9
-
-  reg-names:
-    minItems: 2
-    maxItems: 9
-
-  interrupts:
-    maxItems: 1
-
-required:
-  - compatible
-  - reg
-  - reg-names
-
-allOf:
-  - if:
-      properties:
-        compatible:
-          contains:
-            enum:
-              - qcom,sc7180-llcc
-              - qcom,sm6350-llcc
-    then:
-      properties:
-        reg:
-          items:
-            - description: LLCC0 base register region
-            - description: LLCC broadcast base register region
-        reg-names:
-          items:
-            - const: llcc0_base
-            - const: llcc_broadcast_base
-
-  - if:
-      properties:
-        compatible:
-          contains:
-            enum:
-              - qcom,sc7280-llcc
-    then:
-      properties:
-        reg:
-          items:
-            - description: LLCC0 base register region
-            - description: LLCC1 base register region
-            - description: LLCC broadcast base register region
-        reg-names:
-          items:
-            - const: llcc0_base
-            - const: llcc1_base
-            - const: llcc_broadcast_base
-
-  - if:
-      properties:
-        compatible:
-          contains:
-            enum:
-              - qcom,sc8180x-llcc
-              - qcom,sc8280xp-llcc
-    then:
-      properties:
-        reg:
-          items:
-            - description: LLCC0 base register region
-            - description: LLCC1 base register region
-            - description: LLCC2 base register region
-            - description: LLCC3 base register region
-            - description: LLCC4 base register region
-            - description: LLCC5 base register region
-            - description: LLCC6 base register region
-            - description: LLCC7 base register region
-            - description: LLCC broadcast base register region
-        reg-names:
-          items:
-            - const: llcc0_base
-            - const: llcc1_base
-            - const: llcc2_base
-            - const: llcc3_base
-            - const: llcc4_base
-            - const: llcc5_base
-            - const: llcc6_base
-            - const: llcc7_base
-            - const: llcc_broadcast_base
-
-  - if:
-      properties:
-        compatible:
-          contains:
-            enum:
-              - qcom,sdm845-llcc
-              - qcom,sm8150-llcc
-              - qcom,sm8250-llcc
-              - qcom,sm8350-llcc
-              - qcom,sm8450-llcc
-    then:
-      properties:
-        reg:
-          items:
-            - description: LLCC0 base register region
-            - description: LLCC1 base register region
-            - description: LLCC2 base register region
-            - description: LLCC3 base register region
-            - description: LLCC broadcast base register region
-        reg-names:
-          items:
-            - const: llcc0_base
-            - const: llcc1_base
-            - const: llcc2_base
-            - const: llcc3_base
-            - const: llcc_broadcast_base
-
-additionalProperties: false
-
-examples:
-  - |
-    #include <dt-bindings/interrupt-controller/arm-gic.h>
-
-    soc {
-        #address-cells = <2>;
-        #size-cells = <2>;
-
-        system-cache-controller@1100000 {
-            compatible = "qcom,sdm845-llcc";
-            reg = <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>,
-                <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>,
-                <0 0x01300000 0 0x50000>;
-            reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
-                "llcc3_base", "llcc_broadcast_base";
-            interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
-        };
-    };
diff --git a/Documentation/devicetree/bindings/arm/socionext/socionext,uniphier-system-cache.yaml b/Documentation/devicetree/bindings/arm/socionext/socionext,uniphier-system-cache.yaml
deleted file mode 100644
index 6096c082d56d..000000000000
--- a/Documentation/devicetree/bindings/arm/socionext/socionext,uniphier-system-cache.yaml
+++ /dev/null
@@ -1,101 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/arm/socionext/socionext,uniphier-system-cache.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: UniPhier outer cache controller
-
-description: |
-  UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
-  controller system. All of them have a level 2 cache controller, and some
-  have a level 3 cache controller as well.
-
-maintainers:
-  - Masahiro Yamada <yamada.masahiro@socionext.com>
-
-properties:
-  compatible:
-    const: socionext,uniphier-system-cache
-
-  reg:
-    description: |
-      should contain 3 regions: control register, revision register,
-      operation register, in this order.
-    maxItems: 3
-
-  interrupts:
-    description: |
-      Interrupts can be used to notify the completion of cache operations.
-      The number of interrupts should match to the number of CPU cores.
-      The specified interrupts correspond to CPU0, CPU1, ... in this order.
-    minItems: 1
-    maxItems: 4
-
-  cache-unified: true
-
-  cache-size: true
-
-  cache-sets: true
-
-  cache-line-size: true
-
-  cache-level:
-    minimum: 2
-    maximum: 3
-
-  next-level-cache: true
-
-allOf:
-  - $ref: /schemas/cache-controller.yaml#
-
-additionalProperties: false
-
-required:
-  - compatible
-  - reg
-  - interrupts
-  - cache-unified
-  - cache-size
-  - cache-sets
-  - cache-line-size
-  - cache-level
-
-examples:
-  - |
-    // System with L2.
-    cache-controller@500c0000 {
-        compatible = "socionext,uniphier-system-cache";
-        reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
-        interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
-        cache-unified;
-        cache-size = <0x140000>;
-        cache-sets = <512>;
-        cache-line-size = <128>;
-        cache-level = <2>;
-    };
-  - |
-    // System with L2 and L3.
-    //   L2 should specify the next level cache by 'next-level-cache'.
-    l2: cache-controller@500c0000 {
-        compatible = "socionext,uniphier-system-cache";
-        reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
-        interrupts = <0 190 4>, <0 191 4>;
-        cache-unified;
-        cache-size = <0x200000>;
-        cache-sets = <512>;
-        cache-line-size = <128>;
-        cache-level = <2>;
-        next-level-cache = <&l3>;
-    };
-
-    l3: cache-controller@500c8000 {
-        compatible = "socionext,uniphier-system-cache";
-        reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
-        interrupts = <0 174 4>, <0 175 4>;
-        cache-unified;
-        cache-size = <0x200000>;
-        cache-sets = <512>;
-        cache-line-size = <256>;
-        cache-level = <3>;
-    };
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
index 4a00593b9f7f..89191cfdf619 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
@@ -234,6 +234,7 @@ properties:
     patternProperties:
       "^[a-z0-9]+$":
         type: object
+        additionalProperties: false
 
         properties:
           clocks:
@@ -252,6 +253,9 @@ properties:
               for controlling a power-gate.
               See ../reset/reset.txt for more details.
 
+          power-domains:
+            maxItems: 1
+
           '#power-domain-cells':
             const: 0
             description: Must be 0.