clk: samsung: exynos5433: Add clocks for CMU_APOLLO domain

This patch adds the mux/divider/gate clocks for CMU_APOLLO domain
which generates the clocks for Cortex-A53 Quad-core processsor.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
[s.nawrocki@samsung.com: Renamed pclk_pmu_sysreg_apollo to pclk_sysreg_apollo]
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

1 files changed, 15 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 9e7ed2d43a15..0a7146861a27 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -32,6 +32,8 @@ Required Properties:
     which generates clocks for 3D Graphics Engine IP.
   - "samsung,exynos5433-cmu-gscl"  - clock controller compatible for CMU_GSCL
     which generates clocks for GSCALER IPs.
+  - "samsung,exynos5433-cmu-apollo"- clock controller compatible for CMU_APOLLO
+    which generates clocks for Cortex-A53 Quad-core processor.
 
 - reg: physical base address of the controller and length of memory mapped
   region.
@@ -105,6 +107,10 @@ Required Properties:
 		- aclk_gscl_111
 		- aclk_gscl_333
 
+	Input clocks for apollo clock controller:
+		- oscclk
+		- sclk_bus_pll_apollo
+
 Each clock is assigned an identifier and client nodes can use this identifier
 to specify the clock which they consume.
 
@@ -289,6 +295,15 @@ Example 2: Examples of clock controller nodes are listed below.
 			<&cmu_top CLK_ACLK_GSCL_333>;
 	};
 
+	cmu_apollo: clock-controller@11900000 {
+		compatible = "samsung,exynos5433-cmu-apollo";
+		reg = <0x11900000 0x1088>;
+		#clock-cells = <1>;
+
+		clock-names = "oscclk", "sclk_bus_pll_apollo";
+		clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
+	};
+
 Example 3: UART controller node that consumes the clock generated by the clock
 	   controller.