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| author | Michal Simek <michal.simek@amd.com> | 2023-05-23 09:56:57 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2023-06-05 13:17:36 +0200 |
| commit | a5e0a69dc34b2acf211785e9ad9642c5aaea098b (patch) | |
| tree | 174c7ee16f5de4731a7d3839c0e74c9a64342224 /Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml | |
| parent | 153fc203f68453d9c28e7347420e68fa3665613a (diff) | |
dt-bindings: xilinx: Remove Rajan, Jolly and Manish
Rajan, Jolly and Manish are no longer work for AMD/Xilinx and there is no
activity from them to continue to maintain bindings that's why remove them.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/9b252dd71c82593fa6b137eca2174d9ab6e57f7a.1684828606.git.michal.simek@amd.com
Diffstat (limited to 'Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml index 93ae349cf9e9..5cbb34d0b61b 100644 --- a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml @@ -8,8 +8,6 @@ title: Xilinx Versal clock controller maintainers: - Michal Simek <michal.simek@amd.com> - - Jolly Shah <jolly.shah@xilinx.com> - - Rajan Vaja <rajan.vaja@xilinx.com> description: | The clock controller is a hardware block of Xilinx versal clock tree. It |