diff options
| author | Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> | 2022-02-06 14:58:03 +0100 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> | 2022-02-09 15:34:42 +0100 |
| commit | d98e72b6f9b078c57f9d46dc64a669d02ff2ffcc (patch) | |
| tree | 97022e979ad27c5a17d388c2b5a357600857477e /Documentation/devicetree/bindings/memory-controllers/ddr | |
| parent | 28f818580e49a97876de5c33231fc0e4c3cde2d9 (diff) | |
dt-bindings: memory: lpddr3: adjust IO width to spec
According to JEDEC Standard No. 209-3 (table 3.4.1 "Mode Register
Assignment and Definition in LPDDR3 SDRAM"), the LPDDR3 supports only
16- and 32-bit IO width. Drop the unsupported others.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220206135807.211767-5-krzysztof.kozlowski@canonical.com
Diffstat (limited to 'Documentation/devicetree/bindings/memory-controllers/ddr')
| -rw-r--r-- | Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml index e36f3607e25a..d6787b5190ee 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml @@ -34,10 +34,8 @@ properties: description: | IO bus width in bits of SDRAM chip. enum: - - 64 - 32 - 16 - - 8 manufacturer-id: $ref: /schemas/types.yaml#/definitions/uint32 |