diff options
| author | Miquel Raynal <miquel.raynal@bootlin.com> | 2022-11-14 10:03:06 +0100 |
|---|---|---|
| committer | Miquel Raynal <miquel.raynal@bootlin.com> | 2022-11-17 21:59:16 +0100 |
| commit | c68fc5ed9529987d69d34b367cb390b2285c3ac9 (patch) | |
| tree | 37509806c72bc41fc1c498d488b4d6839a5ede0d /Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand.yaml | |
| parent | eb6fa33657da9526a9e5f43088d80b99a5c0315e (diff) | |
dt-bindings: mtd: sunxi-nand: Add an example to validate the bindings
Copy-paste an existing DT node to ensure the dt_binding_check target
would catch any unforeseen difference.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/linux-mtd/20221114090315.848208-9-miquel.raynal@bootlin.com
Diffstat (limited to 'Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand.yaml')
| -rw-r--r-- | Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand.yaml | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand.yaml b/Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand.yaml index 465aa69f0f10..e7ec0c59bca6 100644 --- a/Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand.yaml +++ b/Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand.yaml @@ -86,4 +86,27 @@ required: unevaluatedProperties: false +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/sun6i-rtc.h> + #include <dt-bindings/clock/sun8i-a23-a33-ccu.h> + #include <dt-bindings/reset/sun8i-a23-a33-ccu.h> + + nand-controller@1c03000 { + compatible = "allwinner,sun8i-a23-nand-controller"; + reg = <0x01c03000 0x1000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_NAND>; + reset-names = "ahb"; + dmas = <&dma 5>; + dma-names = "rxtx"; + pinctrl-names = "default"; + pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>; + #address-cells = <1>; + #size-cells = <0>; + }; + ... |