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| author | Alan Kao <alankao@andestech.com> | 2018-04-20 07:27:49 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2018-06-04 14:02:01 -0700 |
| commit | 178e9fc47aaec1b8952b553444e94802d7570599 (patch) | |
| tree | efa3bc88ef7dfdad550960dc9413ebdcda32727d /Documentation/riscv | |
| parent | 29dcea88779c856c7dc92040a0c01233263101d4 (diff) | |
perf: riscv: preliminary RISC-V support
This patch provide a basic PMU, riscv_base_pmu, which supports two
general hardware event, instructions and cycles. Furthermore, this
PMU serves as a reference implementation to ease the portings in
the future.
riscv_base_pmu should be able to run on any RISC-V machine that
conforms to the Priv-Spec. Note that the latest qemu model hasn't
fully support a proper behavior of Priv-Spec 1.10 yet, but work
around should be easy with very small fixes. Please check
https://github.com/riscv/riscv-qemu/pull/115 for future updates.
Cc: Nick Hu <nickhu@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Signed-off-by: Alan Kao <alankao@andestech.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'Documentation/riscv')
0 files changed, 0 insertions, 0 deletions