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| author | Yang Yingliang <yangyingliang@huawei.com> | 2022-10-18 10:31:47 +0800 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2022-11-09 22:01:31 +0000 |
| commit | 73e770f085023da327dc9ffeb6cd96b0bb22d97e (patch) | |
| tree | cd2bec565e969d8ff3a3cd87454c7cf77c4b8de4 /README | |
| parent | 9abf2313adc1ca1b6180c508c25f22f9395cc780 (diff) | |
soc: sifive: ccache: fix missing iounmap() in error path in sifive_ccache_init()
Add missing iounmap() before return error from sifive_ccache_init().
Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'README')
0 files changed, 0 insertions, 0 deletions