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| author | Kees Cook <keescook@chromium.org> | 2016-07-25 13:50:36 -0700 |
|---|---|---|
| committer | Kees Cook <keescook@chromium.org> | 2016-07-25 13:50:36 -0700 |
| commit | 74e630a7582e6b3cb39559d712a0049f08dea8a0 (patch) | |
| tree | 98a752412dcfc74d802024c1d9e8c541b93174f9 /arch/arc/include/asm/pgtable.h | |
| parent | 35da60941e44dbf57868e67686dd24cc1a33125a (diff) | |
| parent | 523d939ef98fd712632d93a5a2b588e477a7565e (diff) | |
Merge tag 'v4.7' into for-linus/pstore
Linux 4.7
Diffstat (limited to 'arch/arc/include/asm/pgtable.h')
| -rw-r--r-- | arch/arc/include/asm/pgtable.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arc/include/asm/pgtable.h b/arch/arc/include/asm/pgtable.h index 034bbdc0ff61..858f98ef7f1b 100644 --- a/arch/arc/include/asm/pgtable.h +++ b/arch/arc/include/asm/pgtable.h @@ -47,7 +47,7 @@ * Page Tables are purely for Linux VM's consumption and the bits below are * suited to that (uniqueness). Hence some are not implemented in the TLB and * some have different value in TLB. - * e.g. MMU v2: K_READ bit is 8 and so is GLOBAL (possible becoz they live in + * e.g. MMU v2: K_READ bit is 8 and so is GLOBAL (possible because they live in * seperate PD0 and PD1, which combined forms a translation entry) * while for PTE perspective, they are 8 and 9 respectively * with MMU v3: Most bits (except SHARED) represent the exact hardware pos |