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authorMark A. Greer <mgreer@mvista.com>2011-04-01 15:41:26 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-05-12 10:07:00 +0100
commitaf3e4fd37a18f2e5a00175bc96061541d1364a3b (patch)
tree2e68bb99fc917dcf4a4611bf661f018fbbc23851 /arch/arm/boot/compressed/head.S
parent111e9a5ce66e64cbf9cf33a60982f29fd7e224da (diff)
ARM: 6859/1: Add writethrough dcache support for ARM926EJS processor
The ARM kernel supports writethrough data cache via the CONFIG_CPU_DCACHE_WRITETHROUGH option. However, that functionality wasn't implemented in the arch/arm/boot/compressed code. It is now necessary due to a new ARM926EJS processor that has an issue with writeback data cache. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/boot/compressed/head.S')
-rw-r--r--arch/arm/boot/compressed/head.S16
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index adf583cd0c35..ae7ecc286e7a 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -447,7 +447,11 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size
orr r1, r1, #3 << 10
add r2, r3, #16384
1: cmp r1, r9 @ if virt > start of RAM
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+ orrhs r1, r1, #0x08 @ set cacheable
+#else
orrhs r1, r1, #0x0c @ set cacheable, bufferable
+#endif
cmp r1, r10 @ if virt > end of RAM
bichs r1, r1, #0x0c @ clear cacheable, bufferable
str r1, [r0], #4 @ 1:1 mapping
@@ -472,6 +476,12 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size
mov pc, lr
ENDPROC(__setup_mmu)
+__arm926ejs_mmu_cache_on:
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+ mov r0, #4 @ put dcache in WT mode
+ mcr p15, 7, r0, c15, c0, 0
+#endif
+
__armv4_mmu_cache_on:
mov r12, lr
#ifdef CONFIG_MMU
@@ -653,6 +663,12 @@ proc_types:
W(b) __armv4_mpu_cache_off
W(b) __armv4_mpu_cache_flush
+ .word 0x41069260 @ ARM926EJ-S (v5TEJ)
+ .word 0xff0ffff0
+ b __arm926ejs_mmu_cache_on
+ b __armv4_mmu_cache_off
+ b __armv5tej_mmu_cache_flush
+
.word 0x00007000 @ ARM7 IDs
.word 0x0000f000
mov pc, lr