diff options
| author | Jet Li <Jet.Li@ibm.com> | 2020-07-21 20:00:31 +0800 |
|---|---|---|
| committer | Joel Stanley <joel@jms.id.au> | 2020-07-28 09:02:32 +0930 |
| commit | a92532ece75d061a1f950e62e17700eebaffe573 (patch) | |
| tree | 23c0e120814d4d2fb4124304650a00311e21a2ad /arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | |
| parent | 8596ed1502ee2aed39910e58cb2622e98dd433a2 (diff) | |
ARM: dts: aspeed: rainier: Add I2C buses for NVMe use
Adding pca9552 exposes the presence detect lines for the cards and
tca9554 exposes the presence details for the cards.
Signed-off-by: Jet Li <Jet.Li@ibm.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Diffstat (limited to 'arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts')
| -rw-r--r-- | arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 105 |
1 files changed, 105 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index d20cdf3cd55c..e803133f25cd 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -300,6 +300,21 @@ compatible = "atmel,24c64"; reg = <0x51>; }; + + tca9554@40 { + compatible = "ti,tca9554"; + reg = <0x40>; + gpio-controller; + #gpio-cells = <2>; + + smbus0 { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "smbus0"; + }; + }; + }; &i2c1 { @@ -614,6 +629,96 @@ compatible = "atmel,24c64"; reg = <0x51>; }; + + pca1: pca9552@61 { + compatible = "nxp,pca9552"; + reg = <0x61>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@8 { + reg = <8>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@9 { + reg = <9>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@10 { + reg = <10>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@11 { + reg = <11>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@12 { + reg = <12>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@13 { + reg = <13>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@14 { + reg = <14>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@15 { + reg = <15>; + type = <PCA955X_TYPE_GPIO>; + }; + }; + }; &i2c9 { |