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authorJoel Stanley <joel@jms.id.au>2019-09-04 17:02:20 -0700
committerJoel Stanley <joel@jms.id.au>2019-09-04 17:34:31 -0700
commit901d51435c31f9c3147efa64e379bf00208bde01 (patch)
treee8e1fc2847d9eb47707b6da98350e46a5d927abb /arch/arm/boot/dts/aspeed-g4.dtsi
parent49b0f3be0b86292eed6f6aedadf4252131d9c111 (diff)
ARM: dts: aspeed-g4: Add all flash chips
The FMC supports five chip selects, so describe the five possible flash chips. Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
Diffstat (limited to 'arch/arm/boot/dts/aspeed-g4.dtsi')
-rw-r--r--arch/arm/boot/dts/aspeed-g4.dtsi20
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index e465cda40fe7..dffb595d30e4 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -67,6 +67,26 @@
compatible = "jedec,spi-nor";
status = "disabled";
};
+ flash@1 {
+ reg = < 1 >;
+ compatible = "jedec,spi-nor";
+ status = "disabled";
+ };
+ flash@2 {
+ reg = < 2 >;
+ compatible = "jedec,spi-nor";
+ status = "disabled";
+ };
+ flash@3 {
+ reg = < 3 >;
+ compatible = "jedec,spi-nor";
+ status = "disabled";
+ };
+ flash@4 {
+ reg = < 4 >;
+ compatible = "jedec,spi-nor";
+ status = "disabled";
+ };
};
spi: spi@1e630000 {