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authorTony Lindgren <tony@atomide.com>2015-09-14 07:07:28 -0700
committerTony Lindgren <tony@atomide.com>2015-09-14 12:12:15 -0700
commit87ee15ec26000c6edc10e63c415bee1239e042c8 (patch)
treeebf26a07f9f3becacef236d5bc9555c5d33376a5 /arch/arm/boot/dts/dm8148-t410.dts
parent3a2fa775bd1d0579113666c1a2e37654a34018a0 (diff)
ARM: dts: Fix dm814x control base to properly initialize Ethernet PHY
Looks like I made a typo on the control base, all the 81xx SoCs have it at 0x48140000 base. We've just gotten away with the typo as the Ethernet phy was configured by the bootloader on my test system and we're not yet using the pinctrl. In addition to fixing the contol base, we need to also use the right Ethernet phy flags to initialize it. And we are still missing the PLL driver for dm814x and only relying on the divider and mux clocks. Fixes: f3d953ea3721 ("ARM: dts: Add minimal dm814x support") Cc: Matthijs van Duin <matthijsvanduin@gmail.com> Cc: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/dm8148-t410.dts')
-rw-r--r--arch/arm/boot/dts/dm8148-t410.dts4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/dm8148-t410.dts b/arch/arm/boot/dts/dm8148-t410.dts
index 8c4bbc7573df..aecd7dfa2eda 100644
--- a/arch/arm/boot/dts/dm8148-t410.dts
+++ b/arch/arm/boot/dts/dm8148-t410.dts
@@ -19,10 +19,10 @@
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
- phy-mode = "mii";
+ phy-mode = "rgmii";
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
- phy-mode = "mii";
+ phy-mode = "rgmii";
};