ARM: dts: Move .dts files to vendor sub-directories

The arm dts directory has grown to 1559 boards which makes it a bit
unwieldy to maintain and use. Past attempts stalled out due to plans to
move .dts files out of the kernel tree. Doing that is no longer planned
(any time soon at least), so let's go ahead and group .dts files by
vendors. This move aligns arm with arm64 .dts file structure.

There's no change to dtbs_install as the flat structure is maintained on
install.

The naming of vendor directories is roughly in this order of preference:
- Matching original and current SoC vendor prefix/name (e.g. ti, qcom)
- Current vendor prefix/name if still actively sold (SoCs which have
  been aquired) (e.g. nxp/imx)
- Existing platform name for older platforms not sold/maintained by any
  company (e.g. gemini, nspire)

The whole move was scripted with the exception of MAINTAINERS and a few
makefile fixups.

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Michal Simek <michal.simek@amd.com> #Xilinx
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Paul Barker <paul.barker@sancloud.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Wei Xu <xuwei5@hisilicon.com> #hisilicon
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Nick Hawkins <nick.hawkins@hpe.com>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Acked-by: Peter Rosin <peda@axentia.se>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com> #broadcom
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
Acked-by: Patrice Chotard <patrice.chotard@foss.st.com>
Acked-by: Romain Perier <romain.perier@gmail.com>
Acked-by: Alexandre TORGUE <alexandre.torgue@st.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com>
Signed-off-by: Rob Herring <robh@kernel.org>

1 files changed, 0 insertions, 159 deletions

diff --git a/arch/arm/boot/dts/dra76x.dtsi b/arch/arm/boot/dts/dra76x.dtsi
deleted file mode 100644
index 931db7932c11..000000000000
--- a/arch/arm/boot/dts/dra76x.dtsi
+++ /dev/null
@@ -1,159 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include "dra74x.dtsi"
-
-/ {
-	compatible = "ti,dra762", "ti,dra7";
-
-	ocp {
-		target-module@42c01900 {
-			compatible = "ti,sysc-dra7-mcan", "ti,sysc";
-			ranges = <0x0 0x42c00000 0x2000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			reg = <0x42c01900 0x4>,
-			      <0x42c01904 0x4>,
-			      <0x42c01908 0x4>;
-			reg-names = "rev", "sysc", "syss";
-			ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET |
-					 SYSC_DRA7_MCAN_ENAWAKEUP)>;
-			ti,syss-mask = <1>;
-			clocks = <&wkupaon_clkctrl DRA7_WKUPAON_ADC_CLKCTRL 0>;
-			clock-names = "fck";
-
-			m_can0: mcan@1a00 {
-				compatible = "bosch,m_can";
-				reg = <0x1a00 0x4000>, <0x0 0x18FC>;
-				reg-names = "m_can", "message_ram";
-				interrupt-parent = <&gic>;
-				interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
-				interrupt-names = "int0", "int1";
-				clocks = <&l3_iclk_div>, <&mcan_clk>;
-				clock-names = "hclk", "cclk";
-				bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
-			};
-		};
-	};
-
-};
-
-&l4_per3 {
-	target-module@1b0000 {			/* 0x489b0000, ap 25 34.0 */
-		compatible = "ti,sysc-omap4", "ti,sysc";
-		reg = <0x1b0000 0x4>,
-		      <0x1b0010 0x4>;
-		reg-names = "rev", "sysc";
-		ti,sysc-midle = <SYSC_IDLE_FORCE>,
-				<SYSC_IDLE_NO>;
-		ti,sysc-sidle = <SYSC_IDLE_FORCE>,
-				<SYSC_IDLE_NO>;
-		clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>;
-		clock-names = "fck";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x0 0x1b0000 0x10000>;
-
-		cal: cal@0 {
-			compatible = "ti,dra76-cal";
-			reg = <0x0000 0x400>,
-			      <0x0800 0x40>,
-			      <0x0900 0x40>;
-			reg-names = "cal_top",
-				    "cal_rx_core0",
-				    "cal_rx_core1";
-			interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
-			ti,camerrx-control = <&scm_conf 0x6dc>;
-
-			ports {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				csi2_0: port@0 {
-					reg = <0>;
-				};
-				csi2_1: port@1 {
-					reg = <1>;
-				};
-			};
-		};
-	};
-};
-
-&scm_conf_clocks {
-	dpll_gmac_h14x2_ctrl_ck: dpll_gmac_h14x2_ctrl_ck@3fc {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&dpll_gmac_x2_ck>;
-		ti,max-div = <63>;
-		reg = <0x03fc>;
-		ti,bit-shift = <20>;
-		ti,latch-bit = <26>;
-		assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>;
-		assigned-clock-rates = <80000000>;
-	};
-
-	dpll_gmac_h14x2_ctrl_mux_ck: dpll_gmac_h14x2_ctrl_mux_ck@3fc {
-		#clock-cells = <0>;
-		compatible = "ti,mux-clock";
-		clocks = <&dpll_gmac_ck>, <&dpll_gmac_h14x2_ctrl_ck>;
-		reg = <0x3fc>;
-		ti,bit-shift = <29>;
-		ti,latch-bit = <26>;
-		assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
-		assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>;
-	};
-
-	mcan_clk: mcan_clk@3fc {
-		#clock-cells = <0>;
-		compatible = "ti,gate-clock";
-		clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
-		ti,bit-shift = <27>;
-		reg = <0x3fc>;
-	};
-};
-
-&rtctarget {
-	status = "disabled";
-};
-
-&usb4_tm {
-	status = "disabled";
-};
-
-&mmc3 {
-	/* dra76x is not affected by i887 */
-	max-frequency = <96000000>;
-};
-
-&cpu0_opp_table {
-	opp_plus@1800000000 {
-		opp-hz = /bits/ 64 <1800000000>;
-		opp-microvolt = <1250000 950000 1250000>,
-				<1250000 950000 1250000>;
-		opp-supported-hw = <0xFF 0x08>;
-	};
-};
-
-&opp_supply_mpu {
-	ti,efuse-settings = <
-	/* uV   offset */
-	1060000 0x0
-	1160000 0x4
-	1210000 0x8
-	1250000 0xC
-	>;
-};
-
-&abb_mpu {
-	ti,abb_info = <
-	/*uV		ABB	efuse	rbb_m fbb_m	vset_m*/
-	1060000		0	0x0	0 0x02000000 0x01F00000
-	1160000		0	0x4	0 0x02000000 0x01F00000
-	1210000		0	0x8	0 0x02000000 0x01F00000
-	1250000		0	0xC	0 0x02000000 0x01F00000
-	>;
-};