Merge tag 'dt-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC DT updates from Arnd Bergmann:
 "As usual, the bulk of work in the SoC tree goes into DT files, this
  time with a roughly even split between 32-bit and 64-bit SoCs rather
  than the usual mostly 64-bit changes.

  New SoCs:

   - Microchip SAMA7 SoC family based on Cortex-A7, a new 32-bit
     platform based on the older SAMA5 series.

   - Qualcomm Snapdragon SDM636 and SM8150, variations of the existing
     phone SoCs.

   - Renesas R-Car H3e-2G and M3e-2G SoCs, variations of older Renesas
     SoCs.

  New boards:

   - Marvell CN913x reference boards

   - ASpeed AST2600 BMC implementations for Facebook Cloudripper, Elbert
     and Fuji server boards.

   - Snapdragon 665 based Sony Xperia 10II

   - Snapdragon MSM8916 based Xiaomi Redmi 2

   - Snapdragon MSM8226 based Samsung Galaxy S3 Neo

   - NXP i.MX based 32-bit boards:
       - DHCOM based PicoITX
       - DHSOM based DRC0ỉ
       - SolidRun SolidSense
       - SKOV i.MX6 boards.

   - NXP i.MX based 64-bit boards:
       - Nitrogen8 SoM and MNT Reform2
       - LS1088A based Traverse Ten64
       - i.MX8M based GW7902.

   - NVIDIA Jetson TX2 NX Developer Kit

   - 4KOpen STiH418-b2264 development board

   - ux500 based Samsung phones: Gavini, Codina and Kyle

   - TI AM335x based Sancloud BBE Lite

   - ixp4xx dts files to replace all old board files

  Other changes:

   - Treewide fixes for dtc warnings

   - Rockchips i/o domain support

   - TI OMAP/AM3 CPSW switch driver support

   - Improved device support for allwinner, aspeed, qualcomm, NXP,
     nvidia, Renesas, Samsung, Amlogic, Mediatek, ixp4xx, stm32, sti,
     OMAP and actions"

* tag 'dt-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (412 commits)
  arm/arm64: dts: Fix remaining dtc 'unit_address_format' warnings
  ARM: dts: rockchip: Add SFC to RV1108
  arm64: dts: marvell: armada-37xx: Extend PCIe MEM space
  ARM: dts: aspeed: p10bmc: Add power control pins
  ARM: dts: aspeed: cloudripper: Add comments for "mdio1"
  ARM: dts: aspeed: minipack: Update flash partition table
  dt-bindings: arm: fsl: Add Traverse Ten64 (LS1088A) board
  dt-bindings: vendor-prefixes: add Traverse Technologies
  arm64: dts: add device tree for Traverse Ten64 (LS1088A)
  arm64: dts: ls1088a: add missing PMU node
  arm64: dts: ls1088a: add internal PCS for DPMAC1 node
  ARM: dts: imx6qp-prtwd3: configure ENET_REF clock to 125MHz
  ARM: dts: vf610-zii-dev-rev-b: Remove #address-cells and #size-cells property from at93c46d dt node
  ARM: dts: add SKOV imx6q and imx6dl based boards
  dt-bindings: arm: fsl: add SKOV imx6q and imx6dl based boards
  dt-bindings: vendor-prefixes: Add an entry for SKOV A/S
  arm64: dts: imx8mq-reform2: add sound support
  arm64: dts: imx8m: drop interrupt-affinity for pmu
  arm64: dts: imx8qxp: update pmu compatible
  arm64: dts: imx8mm: update pmu compatible
  ...

1 files changed, 32 insertions, 6 deletions

diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi
index 973448c4ad93..52fa211525ce 100644
--- a/arch/arm/boot/dts/exynos5260.dtsi
+++ b/arch/arm/boot/dts/exynos5260.dtsi
@@ -34,42 +34,68 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu@0 {
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+				core1 {
+					cpu = <&cpu1>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&cpu2>;
+				};
+				core1 {
+					cpu = <&cpu3>;
+				};
+				core2 {
+					cpu = <&cpu4>;
+				};
+				core3 {
+					cpu = <&cpu5>;
+				};
+			};
+		};
+
+		cpu0: cpu@0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x0>;
 			cci-control-port = <&cci_control1>;
 		};
 
-		cpu@1 {
+		cpu1: cpu@1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x1>;
 			cci-control-port = <&cci_control1>;
 		};
 
-		cpu@100 {
+		cpu2: cpu@100 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <0x100>;
 			cci-control-port = <&cci_control0>;
 		};
 
-		cpu@101 {
+		cpu3: cpu@101 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <0x101>;
 			cci-control-port = <&cci_control0>;
 		};
 
-		cpu@102 {
+		cpu4: cpu@102 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <0x102>;
 			cci-control-port = <&cci_control0>;
 		};
 
-		cpu@103 {
+		cpu5: cpu@103 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <0x103>;