diff options
| author | Marek Szyprowski <m.szyprowski@samsung.com> | 2015-12-09 09:07:35 +0100 |
|---|---|---|
| committer | Krzysztof Kozlowski <k.kozlowski@samsung.com> | 2016-01-28 21:46:53 +0900 |
| commit | 05053d7a56388d0f44aa388cfe11d1ee2e325f81 (patch) | |
| tree | c2d9378c678b32e535cc28b6a2c0a8ff3db95a64 /arch/arm/boot/dts/exynos5420.dtsi | |
| parent | 4869710caedf5f7cc6a893846e4045d0f35ac737 (diff) | |
ARM: dts: Add GSCL block parent clock management to pm domain on exynos542x
Add support for restoring GScaler parent clocks configuration when GSCL
power domain is turned on.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Diffstat (limited to 'arch/arm/boot/dts/exynos5420.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/exynos5420.dtsi | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 2a405544ea46..bb559d0cd956 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -298,8 +298,10 @@ compatible = "samsung,exynos4210-pd"; reg = <0x10044000 0x20>; #power-domain-cells = <0>; - clocks = <&clock CLK_GSCL0>, <&clock CLK_GSCL1>; - clock-names = "asb0", "asb1"; + clocks = <&clock CLK_FIN_PLL>, + <&clock CLK_MOUT_USER_ACLK300_GSCL>, + <&clock CLK_GSCL0>, <&clock CLK_GSCL1>; + clock-names = "oscclk", "clk0", "asb0", "asb1"; }; isp_pd: power-domain@10044020 { |