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authorAnson Huang <Anson.Huang@nxp.com>2020-05-14 09:08:47 +0800
committerShawn Guo <shawnguo@kernel.org>2020-05-20 10:20:33 +0800
commitd8a6511d988a80dc7b1a83bcc213c6340def3590 (patch)
tree099cc31f8d2d56d68cbe0fa89e8807d7d8d2883c /arch/arm/boot/dts/imx6qdl.dtsi
parent4792ff641cc8993606013d27d84cda59d8cc76c5 (diff)
ARM: dts: imx6qdl: Use nvmem interface to get fuse data
Although ocotp clock is always ON for i.MX6QDL, OCOTP can be accessed directly, but since i.MX6QDL nvmem interface is supported, and fsl,tempmon-data is deprecated, use it instead of getting fuse data by reading ocotp directly, this makes all i.MX6 SoCs aligned. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl.dtsi')
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi11
1 files changed, 10 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 47982889d774..0ddb4dfc9b9b 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -74,7 +74,8 @@
interrupt-parent = <&gpc>;
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
fsl,tempmon = <&anatop>;
- fsl,tempmon-data = <&ocotp>;
+ nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
+ nvmem-cell-names = "calib", "temp_grade";
clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
#thermal-sensor-cells = <0>;
};
@@ -1171,6 +1172,14 @@
cpu_speed_grade: speed-grade@10 {
reg = <0x10 4>;
};
+
+ tempmon_calib: calib@38 {
+ reg = <0x38 4>;
+ };
+
+ tempmon_temp_grade: temp-grade@20 {
+ reg = <0x20 4>;
+ };
};
tzasc@21d0000 { /* TZASC1 */