diff options
| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2018-11-23 20:53:08 +0100 |
|---|---|---|
| committer | Kevin Hilman <khilman@baylibre.com> | 2018-12-04 16:48:13 -0800 |
| commit | 1124d790b431a97dc3c6f4333718bad0f6f3093b (patch) | |
| tree | f399c020e4aadba4da9c04c5c8a091a9663d7713 /arch/arm/boot/dts/meson8.dtsi | |
| parent | e8c276d953d800adced2c6174310320f90c5d432 (diff) | |
ARM: dts: meson8: add the ARM TWD timer
The Meson8 and Meson8m2 SoC are using four ARM Cortex-A9 cores which
come with a "TWD" (Timer-Watchdog) based timer. This adds support for
the ARM TWD Timer on these two SoCs.
Suggested-by: Carlo Caione <carlo@endlessm.com>
[ rebased patch from Carlo, use IRQ_TYPE_EDGE_RISING instead of
IRQ_TYPE_LEVEL_LOW to prevent "GIC: PPI13 is secure or misconfigured"
message during boot, use pre-processor macros to specify the IRQ,
added the correct clock, dropped TWD watchdog node since there's no
driver for it anymore ]
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Diffstat (limited to 'arch/arm/boot/dts/meson8.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/meson8.dtsi | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 28b9f6779993..2b0b3edbd896 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -362,6 +362,13 @@ compatible = "arm,cortex-a9-scu"; reg = <0x0 0x100>; }; + + timer@600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x600 0x20>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; + clocks = <&clkc CLKID_PERIPH>; + }; }; &pwm_ab { |