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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2015-06-02 14:34:35 +0200 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2016-02-19 14:52:23 +0900 |
| commit | d12a384a1b264efd66a50cd5cb311c0d56aff681 (patch) | |
| tree | 8c3a2dd797cb7d0f249ddd243c57b57da796c198 /arch/arm/boot/dts/r8a7793-gose.dts | |
| parent | fdd0dbd8a28612195dfbfb08c404ef5bcfa48e43 (diff) | |
ARM: dts: r8a7794: Add L2 cache-controller node
Add a device node for the L2 cache, and link the CPU nodes to it.
The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7793-gose.dts')
0 files changed, 0 insertions, 0 deletions