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authorKever Yang <kever.yang@rock-chips.com>2014-07-30 13:00:11 -0700
committerHeiko Stuebner <heiko@sntech.de>2014-07-31 05:35:28 +0200
commitbeb4b3f56e342a6ac9b6920bb9b08473c2e37485 (patch)
treed8d4d1056a079bfee36ee02464e09430c8a1567b /arch/arm/boot/dts/rk3288.dtsi
parent83a742b431501c1cf971983fa1911ae5d4b0440c (diff)
ARM: dts: add rk3288 ehci usb devices
rk3288 has two kind of usb controller; this adds the ehci variant for host0 and hsic. At the moment we don't add any phys for these controllers, but the default settings seem to work OK. There is a hardware problem in ohci controller which make it unavailable and host0 controller can only support high-speed devices. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm/boot/dts/rk3288.dtsi')
-rw-r--r--arch/arm/boot/dts/rk3288.dtsi20
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 3ef89512c942..e7cb00873dd4 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -251,6 +251,26 @@
status = "disabled";
};
+ usb_host0_ehci: usb@ff500000 {
+ compatible = "generic-ehci";
+ reg = <0xff500000 0x100>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_USBHOST0>;
+ clock-names = "usbhost";
+ status = "disabled";
+ };
+
+ /* NOTE: ohci@ff520000 doesn't actually work on hardware */
+
+ usb_hsic: usb@ff5c0000 {
+ compatible = "generic-ehci";
+ reg = <0xff5c0000 0x100>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HSIC>;
+ clock-names = "usbhost";
+ status = "disabled";
+ };
+
gic: interrupt-controller@ffc01000 {
compatible = "arm,gic-400";
interrupt-controller;