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authorChris Zhong <zyw@rock-chips.com>2014-12-01 16:52:19 +0800
committerHeiko Stuebner <heiko@sntech.de>2014-12-31 16:18:49 +0100
commiteecfe981cecd82791a72668a416727cb50935bdb (patch)
tree28d50d76b3971d62333942d804d9270082fd14e4 /arch/arm/boot/dts/rk3288.dtsi
parentf74ba117dab86b35e15f8b5a8d913145f3e72ca1 (diff)
ARM: dts: rockchip: add RK3288 suspend support
add pmu sram node for suspend, add global_pwroff pinctrl. The pmu sram is used to store the resume code. global_pwroff is held low level at work, it would be pull to high when entering suspend. reference this in the board DTS file since some boards need it. Signed-off-by: Tony Xie <xxx@rock-chips.com> Signed-off-by: Chris Zhong <zyw@rock-chips.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm/boot/dts/rk3288.dtsi')
-rw-r--r--arch/arm/boot/dts/rk3288.dtsi23
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 3aad41d873d3..2a878a35facc 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -506,6 +506,11 @@
};
};
+ sram@ff720000 {
+ compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
+ reg = <0xff720000 0x1000>;
+ };
+
pmu: power-management@ff730000 {
compatible = "rockchip,rk3288-pmu", "syscon";
reg = <0xff730000 0x100>;
@@ -729,6 +734,24 @@
bias-disable;
};
+ sleep {
+ global_pwroff: global-pwroff {
+ rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ ddrio_pwroff: ddrio-pwroff {
+ rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ ddr0_retention: ddr0-retention {
+ rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
+ };
+
+ ddr1_retention: ddr1-retention {
+ rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
+ };
+ };
+
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,