diff options
| author | Amelie Delaunay <amelie.delaunay@foss.st.com> | 2021-10-06 11:53:55 +0200 |
|---|---|---|
| committer | Alexandre Torgue <alexandre.torgue@foss.st.com> | 2021-10-15 16:51:09 +0200 |
| commit | db7be2cb87ae65e2d033a9f61f7fb94bce505177 (patch) | |
| tree | 5f4019dd7236f46f1b0249b148bba4aaf2ecf272 /arch/arm/boot/dts/stm32mp151.dtsi | |
| parent | 1a9a9d226f0f0ef5d9bf588ab432e0d679bb1954 (diff) | |
ARM: dts: stm32: use usbphyc ck_usbo_48m as USBH OHCI clock on stm32mp151
Referring to the note under USBH reset and clocks chapter of RM0436,
"In order to access USBH_OHCI registers it is necessary to activate the USB
clocks by enabling the PLL controlled by USBPHYC" (ck_usbo_48m).
The point is, when USBPHYC PLL is not enabled, OHCI register access
freezes the resume from STANDBY. It is the case when dual USBH is enabled,
instead of OTG + single USBH.
When OTG is probed, as ck_usbo_48m is USBO clock parent, then USBPHYC PLL
is enabled and OHCI register access is OK.
This patch adds ck_usbo_48m (provided by USBPHYC PLL) as clock of USBH
OHCI, thus USBPHYC PLL will be enabled and OHCI register access will be OK.
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Diffstat (limited to 'arch/arm/boot/dts/stm32mp151.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/stm32mp151.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 6992a4b0ba79..f693a7d24247 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1452,7 +1452,7 @@ usbh_ohci: usb@5800c000 { compatible = "generic-ohci"; reg = <0x5800c000 0x1000>; - clocks = <&rcc USBH>; + clocks = <&rcc USBH>, <&usbphyc>; resets = <&rcc USBH_R>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; |