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authorMaxime Ripard <maxime.ripard@free-electrons.com>2015-10-12 22:21:49 +0200
committerMaxime Ripard <maxime.ripard@free-electrons.com>2015-10-21 22:43:24 +0200
commit6f87abb8cd7dc00701f0a732962420fddbf4b79b (patch)
tree9b27146e740560146a88f321a66061fe507bc6fb /arch/arm/boot/dts/sun5i.dtsi
parent6ee93e127f52d041342b30c8db485b41abcd5bdd (diff)
ARM: sun5i: Add audio PLL
The A13 uses the PLL2 as the audio PLL, which is the parent of all the other audio clocks in the system (i2s, codec, etc.). However, it has a different divider configuration than the A10, hence the difference compatible. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
Diffstat (limited to 'arch/arm/boot/dts/sun5i.dtsi')
-rw-r--r--arch/arm/boot/dts/sun5i.dtsi9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 9ffee9bb70a7..9b03eb95a390 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -102,6 +102,15 @@
clock-output-names = "pll1";
};
+ pll2: clk@01c20008 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun5i-a13-pll2-clk";
+ reg = <0x01c20008 0x8>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll2-1x", "pll2-2x",
+ "pll2-4x", "pll2-8x";
+ };
+
pll4: clk@01c20018 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-pll1-clk";