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authorVenu Byravarasu <vbyravarasu@nvidia.com>2013-05-16 19:42:55 +0530
committerStephen Warren <swarren@nvidia.com>2013-05-17 16:21:08 -0600
commitd400f209b4afe4a196baac276128eccac6a11b31 (patch)
tree48c63ff4f46300bfa80c0118146899b953cd3d24 /arch/arm/boot/dts/tegra20-paz00.dts
parentf722406faae2d073cc1d01063d1123c35425939e (diff)
ARM: tegra: finalize USB EHCI and PHY bindings
The existing Tegra USB bindings have a few issues: 1) Many properties are documented as being part of the EHCI controller node, yet they apply more to the PHY device. They should be moved. 2) Some registers in PHY1 are shared with PHY3, and hence PHY3 needs a reg entry to point at PHY1's register space. We can't assume the PHY1 driver is present, so the PHY3 driver will directly access those registers. 3) The list of clocks required by the PHY was missing some required entries. 4) UTMI PHY Timing parameters are added 5) VBUS control is now specified using a regulator rather than a plain GPIO 6) Added nvidia,is-wired property to indicate whether the device is hard wired on the board, or pluggable. This patch fixes the binding definition to resolve these issues. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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