diff options
author | Thierry Reding <treding@nvidia.com> | 2022-11-22 11:21:18 +0100 |
---|---|---|
committer | Thierry Reding <treding@nvidia.com> | 2023-01-23 12:07:15 +0100 |
commit | d1e34a8abfd6c5ac196f278ac2c5633e3e35ee22 (patch) | |
tree | 53453dc7402826e86b15b1607932b9a0efc9ef1a /arch/arm/boot/dts/tegra20-trimslice.dts | |
parent | 1b929c02afd37871d5afb9d498426f83432e71c2 (diff) |
ARM: tegra: Sort nodes by unit-address, then alphabetically
Nodes in device tree should be sorted by unit-address, followed by nodes
without a unit-address, sorted alphabetically. Some exceptions are the
top-level aliases, chosen, firmware, memory and reserved-memory nodes,
which are expected to come first.
These rules apply recursively with some exceptions, such as pinmux nodes
or regulator nodes, which often follow more complicated ordering (often
by "importance").
While at it, change the name of some of the nodes to follow standard
naming conventions, which helps with the sorting order and reduces the
amount of warnings from the DT validation tools.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra20-trimslice.dts')
-rw-r--r-- | arch/arm/boot/dts/tegra20-trimslice.dts | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index dc51835423a9..1944121e2dd6 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -385,6 +385,16 @@ #clock-cells = <0>; }; + cpus { + cpu0: cpu@0 { + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + gpio-keys { compatible = "gpio-keys"; @@ -462,14 +472,4 @@ <&tegra_car TEGRA20_CLK_CDEV1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; - - cpus { - cpu0: cpu@0 { - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu@1 { - operating-points-v2 = <&cpu0_opp_table>; - }; - }; }; |