diff options
| author | Oscar A Perez <linux@neuralgames.com> | 2019-05-01 13:26:43 +0000 |
|---|---|---|
| committer | Joel Stanley <joel@jms.id.au> | 2019-09-04 17:34:34 -0700 |
| commit | 89b97c429e2e77d695b5133572ca12ec256a4ea4 (patch) | |
| tree | 535e1a0f590d011a97b8eafbcc006b6a4301fb4d /arch/arm/boot | |
| parent | db3a766d2eeeb4ff4a8ce3a55f0a21c65050dd06 (diff) | |
ARM: dts: aspeed-g5: Fixe gpio-ranges upper limit
According to the AST2500/AST2520 specs, these SoCs support up to 228 GPIO
pins. However, 'gpio-ranges' value in 'aspeed-g5.dtsi' file is currently
setting the upper limit to 220 which isn't allowing access to all their
GPIOs. The correct upper limit value is 232 (actual number is 228 plus a
4-GPIO hole in GPIOAB). Without this patch, GPIOs AC5 and AC6 do not work
correctly on a AST2500 BMC running Linux Kernel v4.19
Fixes: 2039f90d136c ("ARM: dts: aspeed-g5: Add gpio controller to devicetree")
Signed-off-by: Oscar A Perez <linux@neuralgames.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/dts/aspeed-g5.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index f360b6c565a5..e8feb8b66a2f 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -301,7 +301,7 @@ compatible = "aspeed,ast2500-gpio"; reg = <0x1e780000 0x1000>; interrupts = <20>; - gpio-ranges = <&pinctrl 0 0 220>; + gpio-ranges = <&pinctrl 0 0 232>; clocks = <&syscon ASPEED_CLK_APB>; interrupt-controller; #interrupt-cells = <2>; |