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authorArnd Bergmann <arnd@arndb.de>2012-02-28 12:33:41 +0000
committerArnd Bergmann <arnd@arndb.de>2012-02-28 12:33:46 +0000
commitabf45ce84c4e36bd64aef20d7df9a79bd5e4b799 (patch)
treef118e135bdd60b680703d1b38c7fdc7b9d7c503d /arch/arm/common
parent082f53c2f573c75a8f1610c587a43b6817e20f90 (diff)
parentb1f91a9ce335eb4e0fef17c10f39a438ac3fce9b (diff)
Merge branch 'imx/defconfig' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc
* 'imx/defconfig' of git://git.linaro.org/people/shawnguo/linux-2.6: (2 commits) ARM: defconfig: imx_v6_v7: build in REGULATOR_FIXED_VOLTAGE ARM: imx: update imx_v6_v7_defconfig (upadte to v3.3-rc5)
Diffstat (limited to 'arch/arm/common')
-rw-r--r--arch/arm/common/it8152.c7
-rw-r--r--arch/arm/common/pl330.c3
2 files changed, 2 insertions, 8 deletions
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
index d1bcd7b13ebc..fb1f1cfce60c 100644
--- a/arch/arm/common/it8152.c
+++ b/arch/arm/common/it8152.c
@@ -320,13 +320,6 @@ err0:
return -EBUSY;
}
-/*
- * If we set up a device for bus mastering, we need to check the latency
- * timer as we don't have even crappy BIOSes to set it properly.
- * The implementation is from arch/i386/pci/i386.c
- */
-unsigned int pcibios_max_latency = 255;
-
/* ITE bridge requires setting latency timer to avoid early bus access
termination by PCI bus master devices
*/
diff --git a/arch/arm/common/pl330.c b/arch/arm/common/pl330.c
index d8e44a43047c..ff3ad2244824 100644
--- a/arch/arm/common/pl330.c
+++ b/arch/arm/common/pl330.c
@@ -1502,12 +1502,13 @@ int pl330_chan_ctrl(void *ch_id, enum pl330_chan_op op)
struct pl330_thread *thrd = ch_id;
struct pl330_dmac *pl330;
unsigned long flags;
- int ret = 0, active = thrd->req_running;
+ int ret = 0, active;
if (!thrd || thrd->free || thrd->dmac->state == DYING)
return -EINVAL;
pl330 = thrd->dmac;
+ active = thrd->req_running;
spin_lock_irqsave(&pl330->lock, flags);