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authorNicolas Pitre <nico@cam.org>2008-09-12 16:11:51 -0400
committerNicolas Pitre <nico@cam.org>2009-03-15 21:01:21 -0400
commit1bb772679ffb0ba1ff1d40d8c6b855ab029f177d (patch)
treec76eb84a6f8df764f0c8e13d84964968c3ab10b7 /arch/arm/include
parent58edb515724f9e63e569536d01ac8d8f8ddb367a (diff)
[ARM] Feroceon: add highmem support to L2 cache handling code
The choice is between looping over the physical range and performing single cache line operations, or to map highmem pages somewhere, as cache range ops are possible only on virtual addresses. Because L2 range ops are much faster, we go with the later by factoring the physical-to-virtual address conversion and use a fixmap entry for it in the HIGHMEM case. Possible future optimizations to avoid the pte setup cost: - do the pte setup for highmem pages only - determine a threshold for doing a line-by-line processing on physical addresses when the range is small Signed-off-by: Nicolas Pitre <nico@marvell.com>
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/kmap_types.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/kmap_types.h b/arch/arm/include/asm/kmap_types.h
index 45def13ee17a..d16ec97ec9a9 100644
--- a/arch/arm/include/asm/kmap_types.h
+++ b/arch/arm/include/asm/kmap_types.h
@@ -18,6 +18,7 @@ enum km_type {
KM_IRQ1,
KM_SOFTIRQ0,
KM_SOFTIRQ1,
+ KM_L2_CACHE,
KM_TYPE_NR
};