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authorJulia Lawall <Julia.Lawall@inria.fr>2022-03-18 11:37:29 +0100
committerFlorian Fainelli <f.fainelli@gmail.com>2022-04-04 11:33:26 -0700
commit0a5ccc9109fa08f2dd6179490f24005e02ee2356 (patch)
tree1d5db2136d4a8b93460bf8fe2a2b6b0773a9a1c9 /arch/arm/mach-bcm/platsmp-brcmstb.c
parent05e3a8cb079b965e4a0759551770bc507dcfa90f (diff)
ARM: brcmstb: fix typos in comments
Various spelling mistakes in comments. Detected with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Diffstat (limited to 'arch/arm/mach-bcm/platsmp-brcmstb.c')
-rw-r--r--arch/arm/mach-bcm/platsmp-brcmstb.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-bcm/platsmp-brcmstb.c b/arch/arm/mach-bcm/platsmp-brcmstb.c
index 4555f21e7077..9b457714a41c 100644
--- a/arch/arm/mach-bcm/platsmp-brcmstb.c
+++ b/arch/arm/mach-bcm/platsmp-brcmstb.c
@@ -59,7 +59,7 @@ static u32 hif_cont_reg;
/*
* We must quiesce a dying CPU before it can be killed by the boot CPU. Because
* one or more cache may be disabled, we must flush to ensure coherency. We
- * cannot use traditionl completion structures or spinlocks as they rely on
+ * cannot use traditional completion structures or spinlocks as they rely on
* coherency.
*/
static DEFINE_PER_CPU_ALIGNED(int, per_cpu_sw_state);