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authorTomasz Figa <t.figa@samsung.com>2014-09-24 01:24:39 +0900
committerKukjin Kim <kgene.kim@samsung.com>2014-10-21 00:06:35 +0900
commit2b9d9c321b5900c7ce82110a81cf3827ca9b33c6 (patch)
tree6809b6da0bdbef8b2ddabf52c6dabc5ad6afdd9a /arch/arm/mach-exynos/firmware.c
parent9c261f89a30010a33c15e6b7cfc7c79ae6bea653 (diff)
ARM: EXYNOS: Add support for firmware-assisted suspend/resume
On a numer of Exynos-based boards Linux kernel is running in non-secure mode under a secure firmware. This means that certain operations need to be handled in special way, with firmware assistance. System-wide suspend/resume is an example of such operations. This patch adds support for firmware-assisted suspend/resume by leveraging recently introduced suspend and resume firmware operations and modifying existing suspend/resume paths to account for presence of secure firmware. Signed-off-by: Tomasz Figa <t.figa@samsung.com> [kgene.kim@samsung.com: rebased] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos/firmware.c')
-rw-r--r--arch/arm/mach-exynos/firmware.c45
1 files changed, 45 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index e8797bb78871..f5e626d55951 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -14,13 +14,20 @@
#include <linux/of.h>
#include <linux/of_address.h>
+#include <asm/cacheflush.h>
+#include <asm/cputype.h>
#include <asm/firmware.h>
+#include <asm/suspend.h>
#include <mach/map.h>
#include "common.h"
#include "smc.h"
+#define EXYNOS_SLEEP_MAGIC 0x00000bad
+#define EXYNOS_BOOT_ADDR 0x8
+#define EXYNOS_BOOT_FLAG 0xc
+
static int exynos_do_idle(void)
{
exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
@@ -69,10 +76,48 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
return 0;
}
+static int exynos_cpu_suspend(unsigned long arg)
+{
+ flush_cache_all();
+ outer_flush_all();
+
+ exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
+
+ pr_info("Failed to suspend the system\n");
+ writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
+ return 1;
+}
+
+static int exynos_suspend(void)
+{
+ if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
+ /* Save Power control and Diagnostic registers */
+ asm ("mrc p15, 0, %0, c15, c0, 0\n"
+ "mrc p15, 0, %1, c15, c0, 1\n"
+ : "=r" (cp15_save_power), "=r" (cp15_save_diag)
+ : : "cc");
+ }
+
+ writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
+ writel(virt_to_phys(exynos_cpu_resume_ns),
+ sysram_ns_base_addr + EXYNOS_BOOT_ADDR);
+
+ return cpu_suspend(0, exynos_cpu_suspend);
+}
+
+static int exynos_resume(void)
+{
+ writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
+
+ return 0;
+}
+
static const struct firmware_ops exynos_firmware_ops = {
.do_idle = exynos_do_idle,
.set_cpu_boot_addr = exynos_set_cpu_boot_addr,
.cpu_boot = exynos_cpu_boot,
+ .suspend = exynos_suspend,
+ .resume = exynos_resume,
};
void __init exynos_firmware_init(void)