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authorAnson Huang <b20788@freescale.com>2014-01-09 16:03:16 +0800
committerShawn Guo <shawn.guo@linaro.org>2014-03-05 10:35:01 +0800
commit751f7e999afcef157527f5f6f06529c93f8a4022 (patch)
tree49dae752f037aa96d2a61ec88ee5179a75c0d86d /arch/arm/mach-imx/common.h
parent848db4a0a17aaf97b8ba5b1f754d635ff622670a (diff)
ARM: imx: add cpuidle support for i.mx6sl
Add cpuidle support for i.MX6SL, currently only support two cpuidle levels(ARM wfi and WAIT mode), and add software workaround for WAIT mode errata as below: ERR005311 CCM: After exit from WAIT mode, unwanted interrupt(s) taken during WAIT mode entry process could cause cache memory corruption. Software workaround: To prevent this issue from occurring, software should ensure that the ARM to IPG clock ratio is less than 12:5 (that is < 2.4x), before entering WAIT mode. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/mach-imx/common.h')
-rw-r--r--arch/arm/mach-imx/common.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index cdbddfa2a42f..b909b689619b 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -140,6 +140,7 @@ void imx_anatop_pre_suspend(void);
void imx_anatop_post_resume(void);
int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
void imx6q_set_int_mem_clk_lpm(void);
+void imx6sl_set_wait_clk(bool enter);
void imx_cpu_die(unsigned int cpu);
int imx_cpu_kill(unsigned int cpu);