diff options
| author | Kevin Hilman <khilman@ti.com> | 2011-03-29 15:57:16 -0700 |
|---|---|---|
| committer | Kevin Hilman <khilman@ti.com> | 2011-09-15 12:08:57 -0700 |
| commit | 24d3194a2c9bc4d2315117915d4d22c395c07fd5 (patch) | |
| tree | d7a5848a3b67f8288fc974bb0b0eab6dacb7ea97 /arch/arm/mach-omap2/vc3xxx_data.c | |
| parent | 08d1c9a3e2dc7a285db7c689c42963d0f5271c1f (diff) | |
OMAP3+: VC: abstract out channel configuration
VC channel configuration is programmed based on settings coming from
the PMIC configuration.
Currently, the VC channel to PMIC mapping is a simple one-to-one
mapping. Whenever a VC channel parameter is configured (i2c slave
addres, PMIC register address, on/ret/off command), the corresponding
bits are enabled in the VC channel configuration register.
If necessary, the programmability of channel configuration settings
could be extended to board/PMIC files, however, because this patch
changes the channel configuration to be programmed based on existing
values from the PMIC settings, it may not be required.
Also note that starting with OMAP4, where there are more than 2
channels, one channel is identified as the "default" channel. When
any of the bits in the channel config for the other channels are zero,
it means to use the default channel. The OMAP4 TRM (at least through
NDA version Q) is wrong in describing which is the default channel.
The default channel on OMAP4 is MPU, not CORE as decribed in the TRM.
Signed-off-by: Kevin Hilman <khilman@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/vc3xxx_data.c')
| -rw-r--r-- | arch/arm/mach-omap2/vc3xxx_data.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/vc3xxx_data.c b/arch/arm/mach-omap2/vc3xxx_data.c index df8bd5ead7e4..f4449eb59841 100644 --- a/arch/arm/mach-omap2/vc3xxx_data.c +++ b/arch/arm/mach-omap2/vc3xxx_data.c @@ -43,6 +43,7 @@ static struct omap_vc_common omap3_vc_common = { .cmd_onlp_shift = OMAP3430_VC_CMD_ONLP_SHIFT, .cmd_ret_shift = OMAP3430_VC_CMD_RET_SHIFT, .cmd_off_shift = OMAP3430_VC_CMD_OFF_SHIFT, + .cfg_channel_reg = OMAP3_PRM_VC_CH_CONF_OFFSET, }; struct omap_vc_channel omap3_vc_mpu = { @@ -51,6 +52,7 @@ struct omap_vc_channel omap3_vc_mpu = { .smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA0_MASK, .smps_volra_mask = OMAP3430_VOLRA0_MASK, .smps_cmdra_mask = OMAP3430_CMDRA0_MASK, + .cfg_channel_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT, }; struct omap_vc_channel omap3_vc_core = { @@ -59,4 +61,5 @@ struct omap_vc_channel omap3_vc_core = { .smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA1_MASK, .smps_volra_mask = OMAP3430_VOLRA1_MASK, .smps_cmdra_mask = OMAP3430_CMDRA1_MASK, + .cfg_channel_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT, }; |