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authorTony Lindgren <tony@atomide.com>2020-01-23 08:38:34 -0800
committerTony Lindgren <tony@atomide.com>2020-01-23 08:38:34 -0800
commit885d21e4956dd70fcd84ed653a8368c9729cfb3e (patch)
tree9a042b092b3a39e9099940a6b52792f31ce6b2c8 /arch/arm/mach-omap2
parenta25e29bd0fe9be33491b3816d2d7b1137d5eeaec (diff)
parentddf664da3b9c6d5c31e0d0c6e5aeb3e65250fdff (diff)
Merge branch 'omap-for-v5.6/ti-sysc-omap45-rng' into omap-for-v5.6/ti-sysc-drop-pdata
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c135
1 files changed, 0 insertions, 135 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 722c641895ba..b7c51ea8c9a6 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -653,32 +653,6 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = {
.opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
};
-/* sha0 HIB2 (the 'P' (public) device) */
-static struct omap_hwmod_class_sysconfig omap44xx_sha0_sysc = {
- .rev_offs = 0x100,
- .sysc_offs = 0x110,
- .syss_offs = 0x114,
- .sysc_flags = SYSS_HAS_RESET_STATUS,
-};
-
-static struct omap_hwmod_class omap44xx_sha0_hwmod_class = {
- .name = "sham",
- .sysc = &omap44xx_sha0_sysc,
-};
-
-static struct omap_hwmod omap44xx_sha0_hwmod = {
- .name = "sham",
- .class = &omap44xx_sha0_hwmod_class,
- .clkdm_name = "l4_secure_clkdm",
- .main_clk = "l3_div_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
/*
@@ -728,103 +702,6 @@ static struct omap_hwmod omap44xx_emif2_hwmod = {
};
/*
- Crypto modules AES0/1 belong to:
- PD_L4_PER power domain
- CD_L4_SEC clock domain
- On the L3, the AES modules are mapped to
- L3_CLK2: Peripherals and multimedia sub clock domain
-*/
-static struct omap_hwmod_class_sysconfig omap44xx_aes_sysc = {
- .rev_offs = 0x80,
- .sysc_offs = 0x84,
- .syss_offs = 0x88,
- .sysc_flags = SYSS_HAS_RESET_STATUS,
-};
-
-static struct omap_hwmod_class omap44xx_aes_hwmod_class = {
- .name = "aes",
- .sysc = &omap44xx_aes_sysc,
-};
-
-static struct omap_hwmod omap44xx_aes1_hwmod = {
- .name = "aes1",
- .class = &omap44xx_aes_hwmod_class,
- .clkdm_name = "l4_secure_clkdm",
- .main_clk = "l3_div_ck",
- .prcm = {
- .omap4 = {
- .context_offs = OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET,
- .clkctrl_offs = OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes1 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_aes1_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod omap44xx_aes2_hwmod = {
- .name = "aes2",
- .class = &omap44xx_aes_hwmod_class,
- .clkdm_name = "l4_secure_clkdm",
- .main_clk = "l3_div_ck",
- .prcm = {
- .omap4 = {
- .context_offs = OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET,
- .clkctrl_offs = OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes2 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_aes2_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/*
- * 'des' class for DES3DES module
- */
-static struct omap_hwmod_class_sysconfig omap44xx_des_sysc = {
- .rev_offs = 0x30,
- .sysc_offs = 0x34,
- .syss_offs = 0x38,
- .sysc_flags = SYSS_HAS_RESET_STATUS,
-};
-
-static struct omap_hwmod_class omap44xx_des_hwmod_class = {
- .name = "des",
- .sysc = &omap44xx_des_sysc,
-};
-
-static struct omap_hwmod omap44xx_des_hwmod = {
- .name = "des",
- .class = &omap44xx_des_hwmod_class,
- .clkdm_name = "l4_secure_clkdm",
- .main_clk = "l3_div_ck",
- .prcm = {
- .omap4 = {
- .context_offs = OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
- .clkctrl_offs = OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__des = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_des_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/*
* 'gpmc' class
* general purpose memory controller
*/
@@ -1735,14 +1612,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
.user = OCP_USER_MPU,
};
-/* l3_main_2 -> sham */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sha0 = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_sha0_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l3_main_2 -> gpmc */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
.master = &omap44xx_l3_main_2_hwmod,
@@ -1958,10 +1827,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
&omap44xx_l4_cfg__usb_tll_hs,
&omap44xx_mpu__emif1,
&omap44xx_mpu__emif2,
- &omap44xx_l3_main_2__aes1,
- &omap44xx_l3_main_2__aes2,
- &omap44xx_l3_main_2__des,
- &omap44xx_l3_main_2__sha0,
NULL,
};